Verilog HDL
229 topics • Page 1 of 5 • 1, 2, 3, 4, 5
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- Help me please
by nominedian » Wed Jun 08, 2011 9:13 pm - 0 Replies
- 56 Views
- Last post by nominedian
Wed Jun 08, 2011 9:13 pm
- Help me please
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- design for receiver on FPGA
by mghanayem » Mon Oct 18, 2010 8:45 pm - 2 Replies
- 927 Views
- Last post by hamster
Mon May 16, 2011 12:23 am
- design for receiver on FPGA
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- CRC module in Verilog
by shahzadhaider » Sat May 14, 2011 10:55 am - 1 Replies
- 65 Views
- Last post by hamster
Mon May 16, 2011 12:20 am
- CRC module in Verilog
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- Passing parameter to `include file
by ericew » Tue May 10, 2011 1:40 am - 0 Replies
- 96 Views
- Last post by ericew
Tue May 10, 2011 1:40 am
- Passing parameter to `include file
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- help with verilog syntax
by uzicohen » Sun Nov 14, 2010 3:29 pm - 1 Replies
- 623 Views
- Last post by rberek
Mon Nov 15, 2010 3:36 pm
- help with verilog syntax
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- HELP : ABOUT 32 BİT ADDER SUBTRACTOR
by WATERFLY » Sat Oct 23, 2010 10:44 pm - 0 Replies
- 713 Views
- Last post by WATERFLY
Sat Oct 23, 2010 10:44 pm
- HELP : ABOUT 32 BİT ADDER SUBTRACTOR
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- UART
by tjtj » Thu May 20, 2010 11:01 am - 2 Replies
- 1279 Views
- Last post by guitarbaka
Mon Oct 18, 2010 2:07 pm
- UART
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- kalman filter
by uzmeed » Fri Oct 08, 2010 9:14 am - 0 Replies
- 716 Views
- Last post by uzmeed
Fri Oct 08, 2010 9:14 am
- kalman filter
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- Trouble instanciating with a bus...
by frcc » Wed Sep 15, 2010 5:25 pm - 1 Replies
- 693 Views
- Last post by Linden
Thu Oct 07, 2010 10:12 pm
- Trouble instanciating with a bus...
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- define include path in .v file?
by NogginBoink » Fri Sep 17, 2010 6:43 pm - 1 Replies
- 774 Views
- Last post by Yassen
Thu Sep 23, 2010 1:28 pm
- define include path in .v file?
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- Free HDL Training
by trickmasterpc » Fri Sep 17, 2010 11:27 pm - 0 Replies
- 797 Views
- Last post by trickmasterpc
Fri Sep 17, 2010 11:27 pm
- Free HDL Training
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- Learn to Design with Verilog
by trickmasterpc » Fri Sep 17, 2010 11:23 pm - 0 Replies
- 793 Views
- Last post by trickmasterpc
Fri Sep 17, 2010 11:23 pm
- Learn to Design with Verilog
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- ISE: Verilog parameters on schematic instantiation
by NogginBoink » Fri Sep 17, 2010 5:11 am - 0 Replies
- 786 Views
- Last post by NogginBoink
Fri Sep 17, 2010 5:11 am
- ISE: Verilog parameters on schematic instantiation
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- Converting fix point to BCD.
by sycho » Sun Sep 05, 2010 7:19 am - 0 Replies
- 924 Views
- Last post by sycho
Sun Sep 05, 2010 7:19 am
- Converting fix point to BCD.
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- Case construct problem
by dethmaShine » Tue Aug 24, 2010 8:46 am - 1 Replies
- 816 Views
- Last post by mcaetano
Thu Aug 26, 2010 2:30 pm
- Case construct problem
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- initial state
by zuzu » Fri Jul 30, 2010 5:09 pm - 1 Replies
- 870 Views
- Last post by Oneironaut
Mon Aug 23, 2010 4:07 am
- initial state
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- floating point package wanted
by Yassen » Tue Aug 10, 2010 1:37 pm - 0 Replies
- 887 Views
- Last post by Yassen
Tue Aug 10, 2010 1:37 pm
- floating point package wanted
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- score board on system verilog
by sarathtm » Mon Aug 09, 2010 5:52 am - 0 Replies
- 878 Views
- Last post by sarathtm
Mon Aug 09, 2010 5:52 am
- score board on system verilog
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- strenghts of signal
by santosh betageri » Thu Aug 05, 2010 11:12 am - 0 Replies
- 851 Views
- Last post by santosh betageri
Thu Aug 05, 2010 11:12 am
- strenghts of signal
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- An edge descriptor error
by dethmaShine » Mon Aug 02, 2010 1:52 pm - 0 Replies
- 972 Views
- Last post by dethmaShine
Mon Aug 02, 2010 1:52 pm
- An edge descriptor error
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- Can you suggest me how to solve this assignment error?
by ali_dehbidi » Wed Jul 28, 2010 6:38 am - 8 Replies
- 1442 Views
- Last post by ali_dehbidi
Mon Aug 02, 2010 1:07 pm
- Can you suggest me how to solve this assignment error?
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- need help on verilog syntax
by Thoma HAUC » Sat Jun 19, 2010 9:09 pm - 11 Replies
- 1735 Views
- Last post by Thoma HAUC
Sun Aug 01, 2010 6:33 pm
- need help on verilog syntax
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- Reciprocal Counter
by crasic » Thu Jul 29, 2010 10:16 am - 0 Replies
- 913 Views
- Last post by crasic
Thu Jul 29, 2010 10:16 am
- Reciprocal Counter
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- Don't know where to begin
by mehanathan » Fri Jul 09, 2010 11:35 pm - 1 Replies
- 969 Views
- Last post by anand
Fri Jul 23, 2010 12:49 pm
- Don't know where to begin
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- Cannot understand the following example on "Repeat Loop
by sarathi.mh » Thu Jul 15, 2010 7:13 pm - 0 Replies
- 895 Views
- Last post by sarathi.mh
Thu Jul 15, 2010 7:13 pm
- Cannot understand the following example on "Repeat Loop
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- Need help on programing an FSM on Spartan 3E 1600
by csimuleac » Sat Jul 03, 2010 7:41 pm - 0 Replies
- 971 Views
- Last post by csimuleac
Sat Jul 03, 2010 7:41 pm
- Need help on programing an FSM on Spartan 3E 1600
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- parameterized module in verilog
by duane » Tue Dec 09, 2008 12:55 pm - 5 Replies
- 4726 Views
- Last post by billt
Mon Jun 28, 2010 10:11 pm
- parameterized module in verilog
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- Help me look at my testbench code
by shihjeff » Mon Jun 21, 2010 9:29 am - 1 Replies
- 932 Views
- Last post by shihjeff
Tue Jun 22, 2010 5:49 am
- Help me look at my testbench code
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- Need help with Verilog GCD calculation code
by element » Sun Jun 20, 2010 7:24 pm - 0 Replies
- 1017 Views
- Last post by element
Sun Jun 20, 2010 7:24 pm
- Need help with Verilog GCD calculation code
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- beginner - question about comparing negative #'s in binary
by jwill » Tue Jun 08, 2010 12:29 am - 6 Replies
- 1669 Views
- Last post by jwill
Fri Jun 18, 2010 11:32 am
- beginner - question about comparing negative #'s in binary
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- FIFO implementation on FPGA SPARTEN 3E
by misstriker » Tue Jun 08, 2010 6:59 am - 12 Replies
- 2631 Views
- Last post by sumgupta
Wed Jun 16, 2010 2:06 pm
- FIFO implementation on FPGA SPARTEN 3E
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- Saving 64-bit variables in byte array in one shot
by Geri » Fri Jun 11, 2010 7:28 am - 0 Replies
- 1032 Views
- Last post by Geri
Fri Jun 11, 2010 7:28 am
- Saving 64-bit variables in byte array in one shot
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- Is it possible to have more than one top module?
by drmatrix » Wed Jun 09, 2010 1:49 pm - 0 Replies
- 927 Views
- Last post by drmatrix
Wed Jun 09, 2010 1:49 pm
- Is it possible to have more than one top module?
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- Noob question about Module Instances....
by tsukanomon » Wed Jun 09, 2010 8:18 am - 0 Replies
- 879 Views
- Last post by tsukanomon
Wed Jun 09, 2010 8:18 am
- Noob question about Module Instances....
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- event based state control
by anand » Sat May 29, 2010 7:51 am - 4 Replies
- 1329 Views
- Last post by anand
Sat Jun 05, 2010 7:26 am
- event based state control
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- How to create a SPI using Verilog. Master and Slave setup.
by dstegs » Mon May 31, 2010 8:06 pm - 0 Replies
- 1090 Views
- Last post by dstegs
Mon May 31, 2010 8:06 pm
- How to create a SPI using Verilog. Master and Slave setup.
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- Please help with for loop problem I think
by randomcodejb » Mon May 31, 2010 7:20 pm - 0 Replies
- 882 Views
- Last post by randomcodejb
Mon May 31, 2010 7:20 pm
- Please help with for loop problem I think
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- Creating a shift register to transfer bits over a line
by dstegs » Sat May 29, 2010 1:34 am - 2 Replies
- 1548 Views
- Last post by NickH
Sat May 29, 2010 12:22 pm
- Creating a shift register to transfer bits over a line
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- Serial N-Tap FIR implementation In Verilog
by hrishi » Tue Apr 13, 2010 10:32 am - 1 Replies
- 1262 Views
- Last post by anand
Sat May 29, 2010 8:05 am
- Serial N-Tap FIR implementation In Verilog
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- timer for counting the number of http get request
by Edmon » Wed May 26, 2010 2:09 am - 0 Replies
- 838 Views
- Last post by Edmon
Wed May 26, 2010 2:09 am
- timer for counting the number of http get request
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- wide shifter for synchonization with the clock
by Yassen » Fri May 14, 2010 11:31 am - 4 Replies
- 1395 Views
- Last post by Yassen
Sat May 15, 2010 7:48 pm
- wide shifter for synchonization with the clock
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- usage of multi phase clocks in a design
by anand » Wed May 05, 2010 1:39 pm - 1 Replies
- 1066 Views
- Last post by Case23
Thu May 06, 2010 9:40 am
- usage of multi phase clocks in a design
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- Can't assign value in the register
by nilytiby » Sat May 01, 2010 11:29 am - 0 Replies
- 995 Views
- Last post by nilytiby
Sat May 01, 2010 11:29 am
- Can't assign value in the register
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- Latch d -> Latch T
by Daniel Minan » Sun Apr 25, 2010 8:02 pm - 1 Replies
- 1203 Views
- Last post by NickH
Mon Apr 26, 2010 11:26 am
- Latch d -> Latch T
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- Need help on Clock
by yongkiat » Wed Apr 21, 2010 3:28 am - 3 Replies
- 1401 Views
- Last post by Yassen
Thu Apr 22, 2010 10:57 am
- Need help on Clock
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- Using " `define X" directive; Verilog syntax quest
by Yassen » Tue Apr 20, 2010 9:18 am - 2 Replies
- 1731 Views
- Last post by Yassen
Tue Apr 20, 2010 7:09 pm
- Using " `define X" directive; Verilog syntax quest
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- What is difference between full case and parallel case?
by Tin » Mon Apr 12, 2010 8:47 am - 1 Replies
- 1374 Views
- Last post by NickH
Tue Apr 20, 2010 9:59 am
- What is difference between full case and parallel case?
229 topics • Page 1 of 5
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