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OK, I didn't know quite where to post this; it's more of an ISE question than a Verilog question but this forum seemed the most applicable given the choices.

I have a Verilog module that uses parameters to define the width of a register.

The top level entity of my ISE project is a schematic. I have an instance of my Verilog module on my schematic.

Question: how can I override the module's parameter in the instance on the schematic?

Thanks!