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I am a tyro at verilog coding. Could someone explain whats going on in this code.

module data_buffer(data_start, data, clock);
parameter cycles=8;
input data_start, clock;
input [15:0] data;
reg [15:0] buffer [0:7];
integer i;
always @ (posedge clock)
begin
if(data_start)
begin
i=0;
repeat (cycles)
begin
@(posedge clock) buffer [i] = data;
i = i+1;
end
end
end
end module

Thanks for helping in Advance.