The favorite HDL language in North America
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- Need Help With Syntax
by TheMuta » Mon Apr 12, 2010 7:43 pm
- 1 Replies
- 1059 Views
- Last post by drmatrix
Thu Apr 15, 2010 6:02 pm
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- Explain the code
by noisepic » Fri Apr 02, 2010 3:52 am
- 3 Replies
- 1373 Views
- Last post by dettus
Fri Apr 09, 2010 12:33 pm
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- vhdl and verilog simulation same bench
by picnanard » Sat Mar 14, 2009 10:14 am
- 5 Replies
- 3467 Views
- Last post by dettus
Fri Apr 09, 2010 12:30 pm
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- beginners verilog bit division question
by masa » Thu Mar 25, 2010 6:07 pm
- 5 Replies
- 1492 Views
- Last post by dettus
Fri Apr 09, 2010 12:26 pm
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- Verilog State Machines: need advice
by DoctorWatson » Tue Feb 10, 2009 2:15 am
- 2 Replies
- 2637 Views
- Last post by flip_flop
Mon Apr 05, 2010 4:29 pm
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- Verilog Gate Level Synthesis
by ankitsrivastava » Mon Apr 05, 2010 2:14 pm
- 0 Replies
- 962 Views
- Last post by ankitsrivastava
Mon Apr 05, 2010 2:14 pm
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- Binary up-down counter. (help needed)
by EUverNE » Fri Sep 11, 2009 10:59 am
- 10 Replies
- 4395 Views
- Last post by ankitsrivastava
Sun Apr 04, 2010 5:25 pm
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- Where can i get verilog codings?
by vairavan.ar » Mon Mar 29, 2010 2:22 pm
- 1 Replies
- 894 Views
- Last post by elpuri
Tue Mar 30, 2010 8:49 pm
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- guys... i need urgent help with my MAC project.
by winston_alf » Fri Mar 26, 2010 2:57 pm
- 1 Replies
- 949 Views
- Last post by rberek
Sat Mar 27, 2010 11:32 am
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- 8 bit MAC unit ... plz help
by winston_alf » Fri Mar 26, 2010 3:04 pm
- 1 Replies
- 851 Views
- Last post by rberek
Sat Mar 27, 2010 11:23 am
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- (without init value) have a constant value of 0 in block
by canonind » Tue Mar 23, 2010 9:34 am
- 1 Replies
- 982 Views
- Last post by elpuri
Wed Mar 24, 2010 4:55 am
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- Yahoouj
by Guest » Sat Mar 20, 2010 3:01 pm
- 0 Replies
- 884 Views
- Last post by Guest
Sat Mar 20, 2010 3:01 pm
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- Verilog Programming Contest
by aj » Wed Feb 17, 2010 1:41 pm
- 0 Replies
- 1107 Views
- Last post by aj
Wed Feb 17, 2010 1:41 pm
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- LP3906 IC question...
by toffee_pie » Thu Jan 21, 2010 2:44 am
- 0 Replies
- 1155 Views
- Last post by toffee_pie
Thu Jan 21, 2010 2:44 am
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- verilog code to comm with a bench supply.
by toffee_pie » Sun Dec 27, 2009 11:08 pm
- 0 Replies
- 1298 Views
- Last post by toffee_pie
Sun Dec 27, 2009 11:08 pm
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- manchester encoder
by thezeek » Mon Dec 21, 2009 6:23 am
- 0 Replies
- 1206 Views
- Last post by thezeek
Mon Dec 21, 2009 6:23 am
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- concatenation.
by thezeek » Thu Dec 17, 2009 4:26 am
- 1 Replies
- 1221 Views
- Last post by thezeek
Thu Dec 17, 2009 4:43 am
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- cordic in verilog
by exin » Wed Dec 09, 2009 4:56 pm
- 4 Replies
- 2803 Views
- Last post by exin
Fri Dec 11, 2009 7:54 am
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- Verilog sine wave generator
by Yassen » Tue Dec 01, 2009 7:48 pm
- 3 Replies
- 2838 Views
- Last post by NickH
Wed Dec 09, 2009 11:25 am
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- debouncer in verilog?
by therekz » Fri Dec 04, 2009 10:50 pm
- 1 Replies
- 1487 Views
- Last post by Yassen
Tue Dec 08, 2009 1:55 pm
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- N00b advice on logical / bitwise operators...?!
by toffee_pie » Tue Nov 17, 2009 8:09 pm
- 5 Replies
- 2100 Views
- Last post by rberek
Wed Nov 18, 2009 5:39 pm
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- LED BLINK
by romacha » Mon May 07, 2007 9:52 pm
- 6 Replies
- 6089 Views
- Last post by thezeek
Fri Nov 13, 2009 4:48 pm
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- newbie help for an ALU design.
by toffee_pie » Fri Oct 30, 2009 10:35 pm
- 8 Replies
- 3118 Views
- Last post by NickH
Thu Nov 12, 2009 10:19 pm
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- Strange coding style?
by Oneironaut » Tue Apr 07, 2009 8:04 pm
- 26 Replies
- 11251 Views
- Last post by Syswip
Thu Nov 12, 2009 2:28 pm
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- shift
by jasonkee » Tue Oct 27, 2009 7:05 am
- 1 Replies
- 1401 Views
- Last post by NickH
Sun Nov 01, 2009 1:25 pm
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- new to Verilog - having problem with easy example
by einarbmag » Mon Sep 14, 2009 9:07 pm
- 1 Replies
- 1421 Views
- Last post by einarbmag
Tue Sep 15, 2009 7:21 am
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- always@(posedge CLK)
by Oneironaut » Sun Sep 13, 2009 7:53 pm
- 2 Replies
- 1984 Views
- Last post by tkbits
Tue Sep 15, 2009 6:35 am
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- UART implementation and clock division
by misstriker » Tue Sep 01, 2009 8:34 am
- 14 Replies
- 5434 Views
- Last post by misstriker
Mon Sep 14, 2009 2:17 am
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- transforming serial controller into pipelining controller
by Faren » Fri Sep 04, 2009 3:51 pm
- 1 Replies
- 1411 Views
- Last post by elpuri
Sat Sep 05, 2009 10:00 am
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- SRAM CONTROLLER
by nazi » Sun Aug 30, 2009 9:46 am
- 1 Replies
- 1952 Views
- Last post by elpuri
Mon Aug 31, 2009 3:18 am
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- Using parameters to enable/disable a signal from module
by StefanLevie » Wed Aug 12, 2009 3:40 pm
- 2 Replies
- 1673 Views
- Last post by alex_lop
Mon Aug 17, 2009 1:13 pm
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- Urgent help needed!!!
by misstriker » Thu Jul 16, 2009 7:00 am
- 33 Replies
- 8892 Views
- Last post by misstriker
Mon Aug 17, 2009 5:51 am
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- oscillating clock
by bluemind » Wed Jul 29, 2009 6:27 am
- 3 Replies
- 2136 Views
- Last post by NickH
Tue Aug 04, 2009 11:06 am
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- Verilog hdl about floating point adder and multiplier?
by ALMODAWAN » Sat Jul 11, 2009 5:25 pm
- 10 Replies
- 5586 Views
- Last post by bluemind
Tue Jul 21, 2009 3:24 pm
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- 8 bit carry look ahead adder
by shaklu » Sat Apr 04, 2009 10:20 am
- 2 Replies
- 4453 Views
- Last post by alex_lop
Fri Jul 17, 2009 3:43 pm
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- 8-bit data to 4-bit encoder
by sickmuse » Thu Jul 16, 2009 2:56 am
- 2 Replies
- 2072 Views
- Last post by sickmuse
Thu Jul 16, 2009 3:51 am
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- How to make synthesizable array of registers?
by alex_lop » Tue May 26, 2009 3:11 pm
- 2 Replies
- 2234 Views
- Last post by alex_lop
Wed Jun 17, 2009 5:38 am
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- Initial statement
by Oneironaut » Tue May 12, 2009 8:43 pm
- 2 Replies
- 2238 Views
- Last post by Oneironaut
Thu May 14, 2009 5:20 pm
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- FIFO variable depth
by hamu » Sun Apr 19, 2009 6:06 am
- 1 Replies
- 2238 Views
- Last post by rberek
Mon Apr 20, 2009 2:58 pm
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- Structural vs behavioural
by juanjo » Wed Apr 15, 2009 8:36 pm
- 1 Replies
- 2180 Views
- Last post by NickH
Thu Apr 16, 2009 8:59 pm
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- Array Assertion Failures on Icarus
by Tsuioku » Tue Mar 24, 2009 12:09 pm
- 1 Replies
- 1986 Views
- Last post by Tsuioku
Wed Mar 25, 2009 4:33 am
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- Test Benches
by duane » Sun Dec 14, 2008 2:13 am
- 4 Replies
- 3383 Views
- Last post by pentium_m
Tue Mar 24, 2009 12:52 pm
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- Is it possible???
by alex_lop » Mon Mar 09, 2009 8:25 am
- 8 Replies
- 4533 Views
- Last post by alex_lop
Wed Mar 18, 2009 4:43 pm
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- UART
by jasonkee » Sun Mar 08, 2009 5:03 am
- 8 Replies
- 5622 Views
- Last post by BTXSistemas
Mon Mar 09, 2009 7:37 pm
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- Verilog 3 to 8 decoder
by zyphirr » Tue Feb 24, 2009 6:33 pm
- 1 Replies
- 4331 Views
- Last post by NickH
Wed Feb 25, 2009 3:52 pm
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- Range expression +: ?
by mrbear » Wed Feb 18, 2009 10:31 am
- 2 Replies
- 2453 Views
- Last post by Yassen
Sat Feb 21, 2009 3:34 pm
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- Reduce the use in Register variable type !
by naofta » Tue Feb 17, 2009 9:58 am
- 1 Replies
- 2801 Views
- Last post by rberek
Tue Feb 17, 2009 2:17 pm
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- C to Verilog (For FPGAs)
by myfpga » Tue Dec 16, 2008 5:26 pm
- 8 Replies
- 4197 Views
- Last post by Ray
Sun Feb 15, 2009 2:36 pm
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- i is not constant
by jasonkee » Sun Feb 08, 2009 5:46 pm
- 2 Replies
- 2401 Views
- Last post by jasonkee
Wed Feb 11, 2009 3:06 am
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- For loop & Generate block
by naofta » Wed Dec 31, 2008 4:36 pm
- 2 Replies
- 2240 Views
- Last post by NickH
Tue Feb 10, 2009 7:47 pm
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