Verilog HDL
229 topics • Page 4 of 5 • 1, 2, 3, 4, 5
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- Another ring oscillator not working
by PBerry » Tue Feb 26, 2008 8:21 pm - 5 Replies
- 3754 Views
- Last post by PBerry
Thu Feb 28, 2008 9:01 pm
- Another ring oscillator not working
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- WebPack 9.2 + asynch. flip-flop
by Yassen » Sun Feb 03, 2008 10:46 am - 11 Replies
- 6090 Views
- Last post by fpga4fun
Fri Feb 15, 2008 8:16 am
- WebPack 9.2 + asynch. flip-flop
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- motion detection!!
by rouffa » Tue Jan 29, 2008 6:41 pm - 3 Replies
- 3094 Views
- Last post by Kristallo
Wed Jan 30, 2008 11:11 pm
- motion detection!!
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- 4X7 segment display
by Tangzenhwai » Fri Jul 13, 2007 8:33 am - 5 Replies
- 4263 Views
- Last post by roddefig
Wed Jan 23, 2008 6:18 pm
- 4X7 segment display
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- Writing to a bus in simulation.
by jcdonelson » Sun Jan 13, 2008 3:30 am - 1 Replies
- 1987 Views
- Last post by jcdonelson
Sun Jan 13, 2008 4:24 pm
- Writing to a bus in simulation.
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- Acessing RAM
by racerxdl » Mon Nov 12, 2007 9:37 pm - 5 Replies
- 3549 Views
- Last post by fpga4fun
Fri Jan 04, 2008 12:44 pm
- Acessing RAM
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- Always@ (posedge clock) executes without clock source.
by PBerry » Fri Dec 14, 2007 3:47 am - 5 Replies
- 3942 Views
- Last post by fpga4fun
Mon Dec 17, 2007 8:50 pm
- Always@ (posedge clock) executes without clock source.
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- $monitor -- Verilog Problem.
by dhavalrules » Wed Oct 24, 2007 7:52 pm - 1 Replies
- 2759 Views
- Last post by rberek
Thu Oct 25, 2007 2:03 pm
- $monitor -- Verilog Problem.
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- Problem in Counter Inferred to latch
by Chet's » Thu Oct 11, 2007 7:07 am - 3 Replies
- 3034 Views
- Last post by tkbits
Wed Oct 17, 2007 4:25 am
- Problem in Counter Inferred to latch
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- "warning: no exact pin location assignment(s)..."
by PooKiPsiT » Mon Jul 23, 2007 7:11 am - 3 Replies
- 3510 Views
- Last post by krolbg
Sun Sep 09, 2007 2:32 am
- "warning: no exact pin location assignment(s)..."
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- Warning: Reduced register "<name>" with stuc
by bigguiness » Fri Aug 24, 2007 10:46 pm - 1 Replies
- 2474 Views
- Last post by Kristallo
Sat Aug 25, 2007 1:31 am
- Warning: Reduced register "<name>" with stuc
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- access internal memory & clocks
by PooKiPsiT » Fri Aug 10, 2007 1:31 pm - 3 Replies
- 2990 Views
- Last post by Kristallo
Thu Aug 23, 2007 10:46 am
- access internal memory & clocks
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- register initialization
by Yassen » Tue Jul 31, 2007 10:28 am - 4 Replies
- 3363 Views
- Last post by tkbits
Wed Aug 01, 2007 2:35 pm
- register initialization
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- Doubt in quartus synthesis attribute --- ramstyle--
by pranavam » Mon Mar 26, 2007 7:10 am - 1 Replies
- 2713 Views
- Last post by Cokacalas
Tue Apr 03, 2007 9:49 am
- Doubt in quartus synthesis attribute --- ramstyle--
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- Xilinx Sensitivity List Problem
by JoelB » Sun Feb 04, 2007 11:06 pm - 1 Replies
- 3786 Views
- Last post by JoelB
Tue Feb 06, 2007 3:49 pm
- Xilinx Sensitivity List Problem
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- Kindly explain difference in Verilog code mentioned below?
by moon_nightingale » Fri Feb 02, 2007 1:55 pm - 1 Replies
- 3078 Views
- Last post by Kristallo
Fri Feb 02, 2007 3:40 pm
- Kindly explain difference in Verilog code mentioned below?
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- How do I bypass top level module for IO in Xilinx verilog?
by nigelk » Wed Dec 27, 2006 5:44 pm - 2 Replies
- 3780 Views
- Last post by Stijena
Tue Jan 23, 2007 1:39 pm
- How do I bypass top level module for IO in Xilinx verilog?
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- From PS2 keyboard code to Binary number conversion
by Victor_li » Mon Jan 22, 2007 5:29 am - 1 Replies
- 3291 Views
- Last post by fpga4fun
Mon Jan 22, 2007 6:30 am
- From PS2 keyboard code to Binary number conversion
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- initial keyword
by outer_space2 » Wed Nov 01, 2006 4:16 pm - 1 Replies
- 3170 Views
- Last post by shoeso
Tue Nov 21, 2006 11:34 am
- initial keyword
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- verilog recommendation question
by vscapcd » Sun Oct 01, 2006 8:46 pm - 2 Replies
- 3920 Views
- Last post by Circumnavicat
Fri Oct 06, 2006 4:47 pm
- verilog recommendation question
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- [VGA] blurry image
by 666boy » Tue May 23, 2006 9:02 am - 2 Replies
- 5268 Views
- Last post by fpga4fun
Wed Aug 09, 2006 11:54 pm
- [VGA] blurry image
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- Newbie simple LED blink question
by Zorro » Fri Jul 28, 2006 9:29 pm - 2 Replies
- 4070 Views
- Last post by Zorro
Mon Aug 07, 2006 10:10 pm
- Newbie simple LED blink question
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- Serial Communication
by uzmeed » Wed Jul 12, 2006 7:56 am - 1 Replies
- 3658 Views
- Last post by Kristallo
Wed Jul 12, 2006 4:42 pm
- Serial Communication
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- Icarus Verilog... Anyone?
by KC2ORW » Wed Nov 23, 2005 7:15 pm - 2 Replies
- 5544 Views
- Last post by pcmcia
Sat Apr 15, 2006 10:48 am
- Icarus Verilog... Anyone?
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- = , <= , plus sequential execution in Verilog
by transistortoaster » Tue Apr 04, 2006 9:48 pm - 5 Replies
- 6933 Views
- Last post by Kristallo
Mon Apr 10, 2006 1:43 am
- = , <= , plus sequential execution in Verilog
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- instruction ready signal
by bbcac » Sun Mar 19, 2006 2:40 am - 1 Replies
- 4093 Views
- Last post by tkbits
Mon Mar 20, 2006 6:10 am
- instruction ready signal
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- tristate in Verilog
by transistortoaster » Mon Mar 13, 2006 7:44 pm - 2 Replies
- 9339 Views
- Last post by tkbits
Wed Mar 15, 2006 7:01 am
- tristate in Verilog
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- Pipelined MAX153 ADC core
by kingtaco » Sat Feb 11, 2006 2:53 am - 1 Replies
- 4202 Views
- Last post by fpga4fun
Sat Feb 11, 2006 4:35 am
- Pipelined MAX153 ADC core
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- Clock Divider
by bbcac » Wed Feb 01, 2006 5:21 am - 6 Replies
- 7480 Views
- Last post by bbcac
Wed Feb 01, 2006 7:06 pm
- Clock Divider
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- Quick Verilog Logic Question
by kierenj » Wed Mar 09, 2005 3:44 pm - 2 Replies
- 5931 Views
- Last post by SkyNET
Wed Feb 01, 2006 5:53 pm
- Quick Verilog Logic Question
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- verilog segment display
by bbcac » Tue Jan 31, 2006 1:57 am - 3 Replies
- 5869 Views
- Last post by Kristallo
Wed Feb 01, 2006 4:50 pm
- verilog segment display
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- Tristate bus interface to FT245BM
by TheMaXX » Sat Dec 17, 2005 2:54 pm - 2 Replies
- 4999 Views
- Last post by DonnaVisitor
Mon Dec 19, 2005 8:56 am
- Tristate bus interface to FT245BM
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- how to output constants: [23,0]data or [7,0]data x clock
by kato » Mon Nov 21, 2005 11:13 pm - 1 Replies
- 4194 Views
- Last post by fpga4fun
Tue Nov 22, 2005 5:28 am
- how to output constants: [23,0]data or [7,0]data x clock
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- quartus reduced register warning
by andrei » Thu Oct 20, 2005 11:26 am - 1 Replies
- 4749 Views
- Last post by andrei
Wed Nov 02, 2005 12:51 pm
- quartus reduced register warning
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- VGA sync modification
by Squant » Sun Sep 25, 2005 1:32 pm - 1 Replies
- 4789 Views
- Last post by Squant
Tue Sep 27, 2005 4:47 pm
- VGA sync modification
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- place array in M4k block
by andrei » Fri Sep 02, 2005 10:54 am - 2 Replies
- 5206 Views
- Last post by Kristallo
Mon Sep 05, 2005 4:06 am
- place array in M4k block
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- Verilog or VHDL?
by GoldenBoy » Mon Aug 29, 2005 11:56 am - 2 Replies
- 5473 Views
- Last post by Kristallo
Mon Aug 29, 2005 5:38 pm
- Verilog or VHDL?
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- Quartus II problem
by Mr.Cod » Mon Jul 11, 2005 4:02 pm - 5 Replies
- 7069 Views
- Last post by fpga4fun
Tue Jul 12, 2005 4:18 pm
- Quartus II problem
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- Module integration, strange state machine behaviour, etc
by kierenj » Fri Jun 24, 2005 11:30 pm - 1 Replies
- 4857 Views
- Last post by kierenj
Mon Jun 27, 2005 7:30 am
- Module integration, strange state machine behaviour, etc
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- Difficulty coding I2C master for Pluto II w/Verilog
by kierenj » Tue Jun 21, 2005 11:01 pm - 5 Replies
- 9383 Views
- Last post by kierenj
Wed Jun 22, 2005 6:03 pm
- Difficulty coding I2C master for Pluto II w/Verilog
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- inputs to/outputs from FPGA board
by thomasc » Fri Jun 17, 2005 10:41 am - 2 Replies
- 5708 Views
- Last post by tkbits
Fri Jun 17, 2005 10:54 pm
- inputs to/outputs from FPGA board
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- post-PAR simulation problem
by thomasc » Thu Jun 16, 2005 6:14 am - 1 Replies
- 4540 Views
- Last post by rwyoung
Thu Jun 16, 2005 1:48 pm
- post-PAR simulation problem
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- How to view internal signals in post synthesis model (ISE)
by thomasc » Mon Jun 13, 2005 1:22 am - 1 Replies
- 4667 Views
- Last post by mrand
Mon Jun 13, 2005 1:39 pm
- How to view internal signals in post synthesis model (ISE)
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- array element assignment problem
by thomasc » Thu May 19, 2005 7:58 am - 3 Replies
- 5770 Views
- Last post by fpga4fun
Fri May 20, 2005 4:30 am
- array element assignment problem
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- New code help
by NewFPGAMan » Sat Mar 05, 2005 1:27 am - 1 Replies
- 4751 Views
- Last post by NewFPGAMan
Sat Mar 05, 2005 2:59 pm
- New code help
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- Code protection
by Mr.Cod » Wed Feb 09, 2005 2:18 pm - 1 Replies
- 4937 Views
- Last post by Kristallo
Thu Feb 10, 2005 11:57 am
- Code protection
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- Clocking question
by Kristallo » Wed Dec 22, 2004 11:31 am - 3 Replies
- 6287 Views
- Last post by fpga4fun
Thu Dec 23, 2004 6:00 pm
- Clocking question
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- ps/2 keyboard
by upiom » Wed Dec 08, 2004 9:07 pm - 1 Replies
- 5385 Views
- Last post by fpga4fun
Wed Dec 08, 2004 9:36 pm
- ps/2 keyboard
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- I am swapping from VHDL to Verilog
by Kristallo » Wed Nov 17, 2004 8:44 am - 5 Replies
- 7542 Views
- Last post by tkbits
Sat Nov 20, 2004 10:13 pm
- I am swapping from VHDL to Verilog
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- initial value in memory
by upiom » Sun Nov 14, 2004 1:12 am - 1 Replies
- 5091 Views
- Last post by fpga4fun
Tue Nov 16, 2004 1:16 am
- initial value in memory
229 topics • Page 4 of 5
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