Verilog HDL
229 topics • Page 5 of 5 • 1, 2, 3, 4, 5
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- Case syntax
by Stijena » Tue Oct 26, 2004 10:47 am - 3 Replies
- 5919 Views
- Last post by Stijena
Tue Nov 09, 2004 2:13 pm
- Case syntax
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- Verilog delays
by stratix » Thu Oct 21, 2004 8:30 pm - 1 Replies
- 5173 Views
- Last post by Kristallo
Fri Oct 22, 2004 4:10 am
- Verilog delays
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- module instantiation
by pirata_01 » Wed Sep 08, 2004 9:37 pm - 2 Replies
- 6185 Views
- Last post by pirata_01
Wed Sep 15, 2004 1:15 am
- module instantiation
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- Syntax error...
by Mr.Cod » Thu Sep 02, 2004 12:46 pm - 1 Replies
- 5436 Views
- Last post by fpga4fun
Thu Sep 09, 2004 4:17 am
- Syntax error...
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- Stepper motor
by Mr.Cod » Tue Jul 27, 2004 5:41 pm - 1 Replies
- 5932 Views
- Last post by bebop603
Wed Aug 04, 2004 9:58 pm
- Stepper motor
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- How can i obtain a .pof file...
by Mr.Cod » Mon Jun 28, 2004 12:00 pm - 1 Replies
- 5422 Views
- Last post by fpga4fun
Mon Jun 28, 2004 6:37 pm
- How can i obtain a .pof file...
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- file I/O in verilog
by stlgrym3 » Tue Jun 15, 2004 10:51 pm - 1 Replies
- 5423 Views
- Last post by fpga4fun
Wed Jun 16, 2004 5:55 pm
- file I/O in verilog
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- question about display ascii character
by stlgrym3 » Mon Jun 14, 2004 6:46 pm - 1 Replies
- 5211 Views
- Last post by fpga4fun
Tue Jun 15, 2004 3:10 pm
- question about display ascii character
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- Instantiating modules
by waddler » Fri Jun 11, 2004 8:45 am - 3 Replies
- 6313 Views
- Last post by fpga4fun
Sun Jun 13, 2004 3:27 am
- Instantiating modules
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- Pseudo-Entropy Generator
by cswiger » Fri Apr 02, 2004 10:23 pm - 4 Replies
- 7495 Views
- Last post by fpga4fun
Thu Apr 08, 2004 8:32 pm
- Pseudo-Entropy Generator
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- verilog newbie stupid question
by statik » Wed Mar 17, 2004 12:07 pm - 1 Replies
- 5562 Views
- Last post by fpga4fun
Wed Mar 17, 2004 5:40 pm
- verilog newbie stupid question
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- First project - Nixie tube clock
by cswiger » Sat Mar 13, 2004 2:53 am - 2 Replies
- 6100 Views
- Last post by fpga4fun
Sat Mar 13, 2004 10:03 pm
- First project - Nixie tube clock
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- LED Bit Bounce version 2
by two_shoes_2002 » Wed Feb 25, 2004 12:24 am - 1 Replies
- 5546 Views
- Last post by fpga4fun
Wed Feb 25, 2004 10:32 pm
- LED Bit Bounce version 2
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- Arrays in Verilog
by Ian » Tue Oct 14, 2003 6:14 pm - 3 Replies
- 6616 Views
- Last post by fpga4fun
Tue Jan 27, 2004 6:15 pm
- Arrays in Verilog
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- The True Meaning of My Code?
by Guest » Wed Feb 02, 2011 8:09 pm - 6 Replies
- 523 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- The True Meaning of My Code?
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- Please see code, Serial to parallel converter in verilog
by arahim » Sat Sep 18, 2010 1:18 pm - 4 Replies
- 1120 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- Please see code, Serial to parallel converter in verilog
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- 1-bit Adder with Cin and Cout problem
by Guest » Sat Feb 05, 2011 5:27 pm - 1 Replies
- 293 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- 1-bit Adder with Cin and Cout problem
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- CRC4 testbench problem
by Guest » Thu Feb 03, 2011 2:42 pm - 0 Replies
- 357 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- CRC4 testbench problem
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- Trouble sending signals from one module to the next.
by Guest » Thu Jan 27, 2011 3:51 pm - 2 Replies
- 349 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- Trouble sending signals from one module to the next.
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- 'include command not working in modelsim
by Guest » Wed Jan 19, 2011 3:00 am - 0 Replies
- 401 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- 'include command not working in modelsim
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- force/release statements
by Guest » Sun Dec 26, 2010 2:58 am - 1 Replies
- 402 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- force/release statements
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- urgent, can anyone please help? counter with enabled..
by Guest » Thu Dec 23, 2010 1:13 am - 0 Replies
- 546 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- urgent, can anyone please help? counter with enabled..
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- who know about the pin planner information that i needed?
by Guest » Thu Dec 23, 2010 1:10 am - 0 Replies
- 423 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- who know about the pin planner information that i needed?
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- how to do this in a testbench?
by Guest » Wed Dec 22, 2010 9:53 am - 0 Replies
- 446 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- how to do this in a testbench?
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- Invalid Module Instantiation
by Guest » Wed Dec 15, 2010 9:19 am - 4 Replies
- 647 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- Invalid Module Instantiation
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- Access internal variables
by Guest » Tue Dec 07, 2010 5:16 pm - 0 Replies
- 486 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- Access internal variables
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- test bench simulation issue
by Guest » Thu Dec 02, 2010 6:08 am - 2 Replies
- 556 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- test bench simulation issue
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- Help with Verilog IRIG-B decoder
by Guest » Mon Nov 15, 2010 7:34 pm - 0 Replies
- 799 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- Help with Verilog IRIG-B decoder
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- [HELP] What is wrong with my code? Syntax Error provided.
by Guest » Tue Feb 08, 2011 1:25 pm - 0 Replies
- 539 Views
- Last post by Guest
Thu Jan 01, 1970 12:00 am
- [HELP] What is wrong with my code? Syntax Error provided.
229 topics • Page 5 of 5
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