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Hi There

I wanted to know whether the usage of both the phases of the clock,i.e. posedge and negedge is synthesizable ?

If so what are the constraints and precautions I need to take?

I keenly await your response

Thank you

hi anand,

yes it is synthesisable, but not within one flipflop. A flipflop can ether use the positive edge or the negative edge. But you can use both types in one design.

It is good code style to not use negative edge, but to have two clock inputs, one positive clock and one negative clock. Then you can use a positive edge flipflop on the negative clock to get the same result. The reason for this coding style is that asic manufacturer cannot verify negative edge flipflops in their production chain.