- Code: Select all
module gcdcalc1(clk, reset, operand_bits_A, operand_bits_B,
result_rdy, result_taken, result_bits_data,agtbw
);
input clk, reset, result_taken;
input [15:0] operand_bits_A;
input [15:0] operand_bits_B;
output reg result_rdy;
output reg [15:0] result_bits_data;
assign agtbw=agtb;
reg [15:0] regAbuf;
reg [15:0] regBbuf;
reg agtb;
reg [15:0] largeop;
reg [15:0] smallop;
initial
begin
regAbuf=operand_bits_A;
regBbuf=operand_bits_B;
end
always @(posedge clk)
begin
agtb<=(regAbuf>regBbuf);
largeop<=agtb?regAbuf:regBbuf;
smallop<=agtb?regBbuf:regAbuf;
regAbuf<=agtb?(regAbuf-regBbuf):regAbuf;
regBbuf<=agtb?(regBbuf-regAbuf):regBbuf;
result_rdy<=(smallop==0)?1:0;
result_bits_data<=largeop;
end
endmodule
And here is the testbench I am using to test the code:
- Code: Select all
module gcdcalctb;
// Inputs
reg clk;
reg reset;
reg [15:0] operand_bits_A;
reg [15:0] operand_bits_B;
reg result_taken;
// Outputs
wire result_rdy;
wire [15:0] result_bits_data;
// Instantiate the Unit Under Test (UUT)
gcdcalc1 uut (
.clk(clk),
.reset(reset),
.operand_bits_A(operand_bits_A),
.operand_bits_B(operand_bits_B),
.result_rdy(result_rdy),
.result_taken(result_taken),
.result_bits_data(result_bits_data),
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
operand_bits_A = 0;
operand_bits_B = 0;
result_taken = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
operand_bits_A=16'HC;
operand_bits_B=16'H12;
end
always
begin
#100;
#5 clk=~clk;
end
endmodule
When running this on Xilinx ISIM however, I am not able to see any change in the output. It stays XXXXXXX throughout the simulation. Why is the output not getting calculated? Please help.