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I want to make a toggle latch from D latch using only data flow only:

module latcht(
input T,
output Led
);

wire d, c, qn;
//1'b0;
assign c = 1'b1;
assign d = q^T;
latchd U1( d, c, q, qn);


endmodule

module latchd(
input D,
input C,
output Q,
output Qn
);


/*assign Q = ((C==1'b1&&D==1'b0)? 1'b0 (C==1'b1 && D==1'b1)?1'b1: Q));
assign Qn = ~Q;*/

endmodule

But when i tested the logic of the Led, it hold at z state all the time

Sorry for my poor english

Hello,

There's no such thing as a "toggle latch". You can have a "toggle flipflop" but you can't have a "toggle latch". If you don't understand why, then you need to think about the difference between a transparent latch (level triggered) and a flipflop (edge triggered)...

Also, your code doesn't do anything, because the assignment statements are inside a /* comment */

"Using only data flow" -- your style of Verilog (trying to use "assign" to define sequential logic) might not be synthesizable. Synchronous RTL style is better for FPGAs.

Regards,

Nick