Latch d -> Latch T

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Latch d -> Latch T

Postby Daniel Minan » Sun Apr 25, 2010 8:02 pm

I want to make a toggle latch from D latch using only data flow only:

module latcht(
input T,
output Led

wire d, c, qn;
assign c = 1'b1;
assign d = q^T;
latchd U1( d, c, q, qn);


module latchd(
input D,
input C,
output Q,
output Qn

/*assign Q = ((C==1'b1&&D==1'b0)? 1'b0 :((C==1'b1 && D==1'b1)?1'b1: Q));
assign Qn = ~Q;*/


But when i tested the logic of the Led, it hold at z state all the time

Sorry for my poor english
Daniel Minan
Posts: 1
Joined: Sun Apr 25, 2010 7:30 pm
Location: Brasil

Postby NickH » Mon Apr 26, 2010 11:26 am


There's no such thing as a "toggle latch". You can have a "toggle flipflop" but you can't have a "toggle latch". If you don't understand why, then you need to think about the difference between a transparent latch (level triggered) and a flipflop (edge triggered)...

Also, your code doesn't do anything, because the assignment statements are inside a /* comment */

"Using only data flow" -- your style of Verilog (trying to use "assign" to define sequential logic) might not be synthesizable. Synchronous RTL style is better for FPGAs.


Posts: 88
Joined: Tue Sep 02, 2008 1:53 pm

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