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Dear all
I have an IS61WV25616BLL device on board and want to add a custom Avalon-MM salve IP to be able to use the ram.
Here is my custom verilog code. But the interface won’t compile. Do you have any idea how to solve the problem? I’m new to verilog and do not know what expert ion should I use. It say’s
Error (10137): Verilog HDL Procedural Assignment error at sram_controller.v(35): object "sram_data" on left-hand side of assignment must have a variable data type
Thanks in advance.

here is the code

Code: Select all

// sram_controller.v

// This file was auto-generated as a prototype implementation of a module
// created in component editor.  It ties off all outputs to ground and
// ignores all inputs.  It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated.  You should check it in
// to your version control system if you want to keep it.

module sram (
      //avalon data bus
      input  wire        clk,                 //             clock.clk
      input  wire [17:0] avs_s0_address,      //                s0.address
      input  wire        avs_s0_read_n,       //                  .read_n
      output wire [15:0] avs_s0_readdata,     //                  .readdata
      input  wire        avs_s0_write_n,      //                  .write_n
      input  wire [15:0] avs_s0_writedata,    //                  .writedata
      input  wire        avs_s0_chipselect_n, //                  .chipselect_n
      input  wire [1:0]  avs_s0_byteenable_n, //                  .byteenable_n
      //sram data bus
      inout  wire [15:0] sram_data,           //         sram_data.export
      output wire [17:0] sram_address,        //      sram_address.export
      output wire        sram_ncs,            //          sram_ncs.export
      output wire        sram_nwe,            //          sram_nwe.export
      output wire        sram_noe,            //          sram_noe.export
      output wire [1:0]  sram_byteenable_n    // sram_byteenable_n.export
   );

   


   always @(avs_s0_address)
   if(avs_s0_write_n)
      assign sram_data=avs_s0_writedata;
   else
      assign sram_data=z;
   
   assign avs_s0_readdata = sram_data;

   assign sram_address = avs_s0_address;

   assign sram_ncs = avs_s0_chipselect_n;

   assign sram_nwe = avs_s0_write_n;

   assign sram_noe = ~avs_s0_readdata;

   assign sram_byteenable_n = avs_s0_byteenable_n;

   // TODO: Auto-generated HDL template

endmodule

Hi!

You cannot do a continuous assignment ("assign") in an "always" block because "assign" means to continuously drive a net. In "always" block, i.e. on event, you must use a "reg"-type net.

Thanks for your reply.
So how can I read and right to an inout bus?
Can you suggest a pseudo code.

Hi!

It's not a problem writing to an "inout" bus. The problem is using an "assign" statement in an "always" block;

You can try this:

assign sram_data = avs_s0_write_n ? avs_s0_writedata : 16'bz;

Thanks for your help.
Yassen Am I reading correctly from sram?

Code: Select all

assign avs_s0_readdata = sram_data;

I mean by using your writing code and using this reading am I doing the right reading and writing to the device?

I have no idea This is because in your design you simple connect some input with given output. This design is purely combinatorial.
For using SRAMs better check with the book "FPGA Prototyping Using Verilog Examples" by Pong P. Chu. A IS61LV25616AL SRAM device is discussed there and some example Verilog code is provided. You can find the code here: Code listing in chapter 11 (the folder should be named "ch11" inside the .zip file). You can download the book from www.gigapedia.org after a free registration and if using "gigapedia" as searching machine.

Hope this helps.

Thanks for your help.
Yassen can you please email the book to me.I can not reach gigapedia.com in here.

ok, it's about 18MB but I can try.
but... I don't know your e-mail

Dear yassen
this is my email
****Edited********!
thanks in advance.