design for receiver on FPGA

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design for receiver on FPGA

Postby mghanayem » Mon Oct 18, 2010 8:45 pm

hi, am beginner in verilog hdl and am workin in project and need to create 8 bits receiver and but the board is comes with 50MHz oscillator and i need it 25MHz so can i do it ?? using verilog and how ?? i need to create counter which could do that !!!!!!

thanx
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Re: design for receiver on FPGA

Postby shahzadhaider » Sat May 14, 2011 11:09 am

mghanayem wrote:the board is comes with 50MHz oscillator and i need it 25MHz so can i do it ??
thanx


I think you can do it using clock dividers.
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Re: design for receiver on FPGA

Postby hamster » Mon May 16, 2011 12:23 am

Or you can use a one bit counter (i.e. a flip flop that toggles every rising clock) and only process on the clock's rising edge and when that flipflop's value is '1'.
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