Serial N-Tap FIR implementation In Verilog

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Serial N-Tap FIR implementation In Verilog

Postby hrishi » Tue Apr 13, 2010 10:32 am


I have implemented parallel 64-tap FIR using verilog.
Now I want to execute all taps serially that is using single tap or MAC hardware unit.

I dont have clear idea how to do it!!

can anybody help me??
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Joined: Tue Apr 13, 2010 10:25 am

Postby anand » Sat May 29, 2010 8:05 am

Hi Hrishi,

I think the hardware for serial implementation of your FIR can be as follows:-

1)A Multiplier and an adder whose precision is dependent on data
2)An accumalator register
3)A counter to keep track of no. of MAC operations remaining.
4)A buffer to store the input samples which gets updated once every 64 clock cycles
5)A buffer to store filter co efficients.
6)An output register.

So basically the sampling rate of your sequence gets reduced by a factor of 64, hence the clock at which you read the new sample also needs to be scaled down by a factor of 64.
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