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Hi guys,

I have implemented a Verilog code that normally works at high clock speed. My design consists of multiple modules, separated in multiple files. For simulation purposes I need to lower the clock a bit, so I am using the compiler directive

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`define

like this:

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`define DEBUG

and then checking

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      `ifdef DEBUG
         // some code
      `else
         // some code
      `endif


The code works fine so far, but I have to go through many files and to change DEBUG / NO_DEBUG every time when I need to simulate.
My question is: Is it possible to declare the `define directive only in the top level module and then to access it from some inner modules? I have tried this, but unsuccessfully. And one more thing: I know that Verilog can read the <include ...> statement. Can you give me some example of using <include ...>. Is it suitable for synthesis? Preferably, I am using Verilog 2001 and 2005.

Thank you
Yassen

[Well traditionally, Verilog would concatenate all source files together, so if you `define something the first file, it would be seen everywhere. However, this antique behaviour can't be relied upon!]

Yes, you can `include a file from every source file, just put

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`include "definitions.vh"

at the top of each Verilog source file, and make a file "definitions.vh" in the same directory, containing:

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`define DEBUG

If you're using an IDE you may need to register the new file with the IDE as a "header file". Then just comment and uncomment the `define, to change behaviour. It should work for synthesis.

Or, depending on what tools you're using, there may be a way to specify some `defines on the command line, or in some top-level project configuration. It might already define certain symbols automatically, for simulation or synthesis?

Regards,

Nick

Hi, Nick!

Thank you for your help. I have just tried this and it worked perfect. There's always something good to learn
I am using Xilinx ISE - it does not accept the '.vh' file extension, but obviously any extension works, so now I am happy
And, yes, I've heard about that Verilog "tradition" that you have mentioned, but with my design tool and Verilog version the tradition is not what it is.

Yassen