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Guys!

To avoid metastability I need to synchronize external inputs of my CPLD with it's clock domain. Such example have already been done in the SPI project in current website:

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// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr;  always @(posedge clk) SCKr <= {SCKr[1:0], SCK};

My question is:
How can I synchronize 64 inputs of my CPLD design simultaneously, i.e. whithout instatiating the above code 64 times. I need help for something like 64-bits-wide X 3-bits-deep shift register to sync. with the CPLD clock all my inputs.

Thank you!

Yes, you just have to turn the above code "sideways", like this:

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reg [63:0] sync0, sync1, sync2;
always @(posedge clk) begin
  sync0 <= signals;
  sync1 <= sync0;
  sync2 <= sync1;
end


You probably know this already, but: if the signals are all changing at the same time, it's not guaranteed to give a "consistent snapshot".

Regards,

Nick

Hi, Nick!

Thank you very much. Your code means that I have to transform my 3-bit shifter to 3 64-bit registers and to shift the signals simultaneously. Great!

But what do you mean with your last sentece?

if the signals are all changing at the same time, it's not guaranteed to give a "consistent snapshot"

My problem is: I have a 64-bit input port which signals are of course external to the logic. So I have to make these signals synchronous with the CPLD clock domain. I want to generate an interrupt signal (a flag) whenever ANY of those 64 bits change at any time. It is needed for to be able to inform the external circuit that something happens. Do you think it's feasible? I intend to write something like this:

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module oneshot(
   input clk,            //   master clock = 50MHz
   input [63:0] osin,   // my 64-bit input port
   output reg osout);   //   one-shot -> my interrupt signal
   
   reg q;

   always @(osin or posedge osout)
      begin
         if(osout)
            q <= 0;
         else
            q <= 1;
      end

   always @(posedge clk)
      osout <= q;

endmodule

This will be a one-shot circuit that produces a single pulse every time a bit from the input port changes. Below is the simulation result for the one-shot:


Thanks once more for your help!
Yassen

Hi there,

I just meant, if two inputs change simultaneously, the circuit might not "see" both changes in exactly the same clock cycle (one of them might be seen one cycle later than the other).

But if you just want to detect a change on any input, it's no problem.

Nick

Copy that!
Thank you very much one more time. You really helped me a lot.

Yassen