fpga4fun.com

Hi, i`m trying to crate an FSM on a Spartan 3E-1600, an so far I didn`t do nothing. I`ve found some codes on internet but most of all are wrong. In my last reserches i`ve found an examples describing an FSM but dont know what its doing, i`m using Xilinx ISE 11 and the HDL is Verilog. I`m still a beginer with FPGA`s and i have a project in few months and want to create something. If anyone knows someting about this program please post an answear, it will be nice to hear from you guys. And i`m needing an .UCF file cuz i dont know how to crate it.

P.S. I`m sorry for my bad english, hope my mistakes in text were few and you could understand what i want.

Here is the code file for this FSM.


module FSM_Example (
// Inputs:
Clock, // Master clock
Reset, // Master reset (active high)
A,
B,
C,
// Outputs:
D,
E,
F
);

// Port mode declarations:
// Inputs:
input Clock;
input Reset;
input A;
input B;
input C;

// Outputs:
output D;
output E;
output F;
// Registered identifiers:
// NOTE: Remove (or comment out) each line for which the 'assign' method is used
reg D;
reg E;
reg F;
// Functionality:
// Declare parameters to represent the state bit patterns
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
parameter s4 = 3'b100;

// Declare outputs of each circuit block
reg [2:0] State, NextState;


// State register
always @ (posedge Clock or posedge Reset)
if (Reset)
r$State <= p$s0;
else
State <= NextState;

// Output decoder
always @ (State) begin
D <= (State == s1 || State == s4);
E <= (State == s2);
F <= (State == s3);
end

// Next state decoder
always @ (State or A or B or C)
case (State)
s0: NextState <= (A) ? s4 : s1;
s1: NextState <= s2;
s2: NextState <= s3;
s3: if (B)
NextState <= (C) ? s4 : s0;
else
NextState <= s3;
s4: NextState <= s0;
default: NextState <= s0;
endcase


endmodule


And the folowing code is the TB for this code.

module FSM_Example_TESTBENCH;
// Input stimulus:
reg Clock;
reg Reset;
reg A;
reg B;
reg C;
// Output connections:
wire D;
wire E;
wire F;
// Set the maximum number of characters in the statename string
parameter MaxChars = 4;
// Create the "StateName" identifier (must declare the total
// number of bits... eight bits per character)
reg [8*MaxChars-1 : 0] StateName;
//Instantiate the DUT (device under test):
FSM_Example DUT (
// Inputs:
.Clock ( Clock ),
.Reset ( Reset ),
.A ( A ),
.B ( B ),
.C ( C ),

// Outputs:
.D ( D ),
.E ( E ),
.F ( F )
);

// Specify input stimulus:
initial begin

// Initial values for input stimulus:
Clock = 0;
Reset = 1;

A = 1'b0;
B = 1'b0;
C = 1'b0;

// Take out of reset
#10 Reset = 0;

// Wait until state s3, wait another
// period, then assert C
wait (DUT.State==DUT.s3) #10 C = 1;

// Deassert C
#10 C = 0;

// Assert B, then deassert
#10 B = 1;
#10 B = 0;

// Assert C
#10 C = 1;

// Wait until state s3, wait another
// period, then assert B
wait (DUT.State==DUT.s3) #10 B = 1;

// Wait until state s0 then stop
wait (DUT.State==DUT.s0) #10 $finish;

end

// Template for master clock. Uncomment and modify signal name as needed.
// Remember to set the initial value of 'Clock' in the 'initial' block above.
always #5 Clock = ~Clock;

// Create human-readable labels for current state
always @ (DUT.State)
case (DUT.State)
3'b000: StateName = "S0";
3'b001: StateName = "S1";
3'b010: StateName = "S2";
3'b011: StateName = "S3";
3'b100: StateName = "S4";
default:StateName = "??";
endcase


endmodule