help with verilog syntax

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help with verilog syntax

Postby uzicohen » Sun Nov 14, 2010 3:29 pm

Hi All,
lately i've encounter rather new verilog syntax for which i cannot find description or user guide.
i'm refereing to the exshastive use of colon with another operator
for example:
t1:=x(0) + x(8);
Data[j][SigDataCnt[j]*8+7-:8] <=TestCounter[7:0];

So if anyone can provide link to manual of this coding style i'd be thankful.

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Joined: Sun Oct 03, 2010 4:34 pm

Postby rberek » Mon Nov 15, 2010 3:36 pm

I have never seen the first usage, but the second is a variable part select first introduced in Verilog-2001. It is a shorthand way of saying:

Code: Select all

Data[j][SigDataCnt[j]*8+7 : SigDataCnt[j]*8] <=TestCounter[7:0];

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Joined: Wed May 23, 2007 5:32 pm

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