Well I am a beginner at FPGAs. I need to develop a simple parallel in serial out module.The data will be serially out through UART. I have written a code but I am not able to run it on Altera Cyclone 2 board. Any body please help me out.
module transmit(clk,din,dout,ledout);
input clk;
input [7:0] din;
output dout;
reg dout;
always @(posedge clk)
begin
#0 dout=1'b0; //start bit
#104166 dout=din[0];
#104166 dout=din[1];
#104166 dout=din[2];
#104166 dout=din[3];
#104166 dout=din[4];
#104166 dout=din[5];
#104166 dout=din[6];
#104166 dout=din[7];
#104166 dout=1'b1; //stop bit
end
endmodule