The favorite HDL language in North America


Postby tjtj » Thu May 20, 2010 11:01 am

Well I am a beginner at FPGAs. I need to develop a simple parallel in serial out module.The data will be serially out through UART. I have written a code but I am not able to run it on Altera Cyclone 2 board. Any body please help me out.

module transmit(clk,din,dout,ledout);
input clk;
input [7:0] din;
output dout;
reg dout;

always @(posedge clk)
#0 dout=1'b0; //start bit
#104166 dout=din[0];
#104166 dout=din[1];
#104166 dout=din[2];
#104166 dout=din[3];
#104166 dout=din[4];
#104166 dout=din[5];
#104166 dout=din[6];
#104166 dout=din[7];
#104166 dout=1'b1; //stop bit
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Postby WadeH » Thu May 20, 2010 11:27 pm

You are using simulation constructs to do something that will be synthesized: big difference.
All those 104,166 nanosecond periods that you decreed to exist will have to be generated by Verilog hardware that you will have to write (or steal.)
You should look at as a starting-point
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Joined: Fri Apr 22, 2005 3:17 pm


Postby guitarbaka » Mon Oct 18, 2010 2:07 pm

A little late but you can find a UART transmitter tutorial here. It is pretty easy to follow. It looks like this website is currently being constructed as tutorial based. ... &Itemid=12
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Joined: Mon Oct 18, 2010 2:03 pm

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