Help me look at my testbench code

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Help me look at my testbench code

Postby shihjeff » Mon Jun 21, 2010 9:29 am

Hi,
I am doing the example for serial interface rs232 to FPGA (from fpga4fun). Right now I am trying to write a testbench code to simulate before downloading to FPGA. While I run the simulation, I can't get anything about GPout. I don't know which part is wrong. Thanks very much.
Here is my code:
`timescale 1ns / 1ps
module serialfun_tb;

// Inputs
reg clk;
reg RxD;
reg [7:0] GPin;

// Outputs
wire TxD;
wire [7:0] GPout;

// Instantiate the Unit Under Test (UUT)
serialfun uut (
.clk(clk),
.RxD(RxD),
.TxD(TxD),
.GPout(GPout),
.GPin(GPin)
);

initial begin
// Initialize Inputs
clk = 0;
RxD = 0;
GPin = 0;

#10;
clk = 1;
RxD = 1;
GPin = 8'b0000_0001;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0000_0001;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0000_0010;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0000_0010;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0000_0100;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0000_0100;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0000_1000;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0000_1000;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0001_0000;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0001_0000;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0010_0000;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0010_0000;
#10;
clk = 1;
RxD = 1;
GPin = 8'b0100_0000;
#10;
clk = 0;
RxD = 1;
GPin = 8'b0100_0000;
#10;
clk = 1;
RxD = 1;
GPin = 8'b1000_0000;
#10;
clk = 0;
RxD = 1;
GPin = 8'b1000_0000;

// Add stimulus here

end

endmodule
shihjeff
 
Posts: 2
Joined: Mon Jun 21, 2010 9:22 am

Postby shihjeff » Tue Jun 22, 2010 5:49 am

I did something revise for my testbench code, but I still cant get anything about GPout.

module serialfun_tb;


reg clk;
reg RxD;
reg [7:0] GPin;

wire TxD;
wire [7:0] GPout;
wire [7:0] RxD_data;
wire RxD_data_ready;
parameter Baud8GeneratorAccWidth = 16;
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
parameter clkper=174;

serialfun uut (
.clk(clk),
.RxD(RxD),
.TxD(TxD),
.GPout(GPout),
.GPin(GPin)
);

initial begin

clk = 1;
RxD = 0;
GPin = 0;
end

always
begin
#(clkper/2);
clk <= ~clk;
end

always
begin
#(clkper*1.5);
RxD <= ~RxD;
end

endmodule
shihjeff
 
Posts: 2
Joined: Mon Jun 21, 2010 9:22 am


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