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I'm trying to write generic, non-vendor-specific Verilog code.

I'd like to build a library of building blocks and put them in an include folder, then include them in my top level .v file.

I'd like to be able to specify the include path in Verilog. Is this possible?

I've tried something like:

Code: Select all

`define _INCLUDE_PATH_ c:\somefolder
`include _INCLUDE_PATH_\mymodule.v


I've tried various permutations of quotation marks around the path to no avail.

Can I accomplish my goal in Verilog?

Try this one - for me it works quite well:
`include "yourfile.v"