Noob question about Module Instances....

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Noob question about Module Instances....

Postby tsukanomon » Wed Jun 09, 2010 8:18 am

Hello Guyz, i am having a problem with some module instances in verilog, because some input of my instances are the outputs of another module instance, and i dont know how to get that work all together, because individually they work fine, i am using the quartus II so if u could help me i would be thks .

Code: Select all
module UC_Exec
   input [4:0] opcode,
   input [1:0] cond,
   input [2:0] op2,
   input [2:0] op1,
   input [15:0]addr,
   input clk,
   output over,
   output signed [15:0] result

// Conexoes

   wire [15:0] waddr = addr;
   wire [4:0] wopc = opcode;
   wire [2:0] wop1 = op1;
   wire [2:0] wop2 = op2;
   wire [1:0] wcond = cond;
   wire overflow = over;
   wire resneg, reszero;
   wire signed [15:0] wdataout1, wdataout2, wularesult, wutdresult;

// Codigo

   ula_art  ula   (wdataout1,wdataout2,wopc,clk,wularesult,overflow,resneg,reszero);
   utd      uttd   (/*wdataout1*/waddr,wopc,clk,wutdresult);
   bancoreg bdreg ((wularesult | wutdresult),wop1,wop1,wop2,clk,wopc,wdataout1,wdataout2);
   assign result = (wularesult | wutdresult);
   assign over = (overflow);

So its like i said, in this case the wires wdataout1 and wdataout2 are inputs for my ULA instance but they are my outputs for BDREG instance because i need data wich comes from my BDREG in the entrance of my ULA and UTTD, i think thats the problem but i dont know how to fix that...what do u sugest guyz?? thks a lot.
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Joined: Wed Jun 09, 2010 8:10 am

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