- Code: Select all
//Case construct:
always @(posedge clk50 or posedge reset)
begin
if(reset)
begin
flow_trans_Address <= 8'h00;
flow_trans_Data[7:0] <= 8'h00;
flow_trans_Data[15:8] <= 8'h00;
flow_trans_WriteMe <= 8'h00;
flow_trans_ReadMe <= 8'h00;
end
if(flow_WriteStrb)
begin
case(flow_Address)
8'h10 : flow_trans_Address[7:0] <= flow_DataIn;
8'h11 : flow_trans_Address[9:8] <= flow_DataIn;
8'h20 : flow_trans_Data[7:0] <= flow_DataIn;
8'h30 : flow_trans_Data[15:8] <= flow_DataIn;
8'h40 : flow_trans_WriteMe <= flow_DataIn;
8'h50 : flow_trans_ReadMe <= flow_DataIn;
default : flow_trans_Address[7:0] <= 8'h11;
endcase
end
end
The declarations are:
- Code: Select all
module flowhandler(clk50,
reset,
flow_Address,
flow_DataIn,
flow_WriteStrb,
flow_trans_Address,
flow_trans_Data,
flow_trans_WriteMe,
flow_trans_ReadMe
);
//inouts
input clk50;
input reset;
input[7:0] flow_Address;
input[7:0] flow_DataIn;
input flow_WriteStrb;
output flow_trans_Address;
output flow_trans_Data;
output flow_trans_WriteMe;
output flow_trans_ReadMe;
reg[9:0] flow_trans_Address;
reg[15:0] flow_trans_Data;
reg flow_trans_WriteMe;
reg flow_trans_ReadMe;
The errors are:
The logic for <flow_trans_Address[9]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.