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hi everyone,

i'm new to verilog, and now i've got a question.What is difference between Verilog full case and parallel case?

Thanks.
Tin

Hi,

They are non-standard extensions for Synopsys tools.
- "full_case" asserts that at least one of the cases is always true (otherwise, we don't care). It's used to avoid latches. It's roughly the same as "default: output = 'bX;"
- "parallel_case" asserts that no more than one case is ever true (otherwise, we don't care). It's used to simplify logic for "one hot" encoding.

The trouble is: they're not standard, they're not necessary, and they can make synthesis and simulation behave differently.

You might find this interesting -> http://kunalvyas.com/Documents/fullcase%20and%20parallel%20case.pdf

Nick