fpga4fun.com
where FPGAs are fun!
Skip to content
Task
The favorite HDL language in North America
Post a reply
1 post • Page
1
of
1
Task
by
jasonkee
» Thu Jan 06, 2011 7:52 am
Inside the testbench, can we have always block inside the task? Will it be forever loop and task can't be ended?
e.g.
call task sendpacket;
call another task;
task sendpacket;
always @ (*)
if ()
else ()
endtask
jasonkee
Posts:
12
Joined:
Sat Feb 07, 2009 2:18 am
Top
Post a reply
1 post • Page
1
of
1
Return to Verilog HDL