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Hi there

I wanted to design a hardware for an event based state control,

is there a provision in verilog to trigger a construct on occurrence of an event?

Is it synthesizable ?

If so could you please let me know the syntax?

Thank you and regards:-)

Verilog simulation is entirely based on events. An event occurs whenever any signal changes. In simulation, you can also use "named events" which are triggered by the -> operator.
An event-triggered process has the form "always @(event1 or event2 ...) begin ... end". [You can look up the detailed syntax online.]

However, for processes to be synthesizable, they have to be either combinational (i.e. triggered by a change in any input) or flip-flop based (i.e. triggered by a single rising or falling clock edge, with optional reset). Other constructions are not generally synthesizable.

So it may help to adapt your design to a clock-synchronous one.

You can have a small number (typically up to 8) of different clock domains within an FPGA.

Regards,

Nick

Hi Nick,

Thank you for the reply.

This is a more specific description of my problem :-

-> once at the posedge of EVENT1 I start my counter
-> once my counter counts up to 255 I need to trigger off another EVENT2,
->Suppose EVENT1 occurs within 255 count I need to restart the counter
->Suppose EVENT2 is triggered it has to go on and complete itself.
->EVENT1 is supposed to be asynchronous where as EVENT2 is synchronous
->Once EVENT2 is complete, I should wait for next EVENT1 pulse during the course of which I start off another counter which has to count till 127,If EVENT1 pulse does not arrive I start off EVENT2 again.

Any suggestions how to write a Code that is easy to debug for the above described problem?

Thank You:-)

Well, like I hinted above: if you want it to be synthesizable, it should be clock-based. So the quick answer is: forget about events and think about a clocked state machine.

I assume EVENT1 is an asynchronous input? So I would put it through a shift register of 3 flipflops. The first 2 are to synchronize it to the clock domain; the 3rd flop is to detect changes. Maybe like this:

Code: Select all

reg sr[2:0];
always @(posedge clk) sr <= { sr[1:0], input1 };
wire rising_edge_seen = sr[1] & ~sr[2];


Then maybe use "rising_edge_seen" as an input to a synchronous state machine (which would also manage the counter: strictly speaking, the counter is part of its state).

I'm not going to go into any more detail, because I didn't understand your description. I didn't know what you meant by EVENT2 having to "go on and complete itself". Events are atomic. It sounds more like a timer than an event.

Sorry if that's not the kind of answer you wanted, but I don't think there's any better way to design it, than as a state machine with a built-in counter.

Regards,

Nick

Thank you nick, Things are somewhat clearer to me after your previous reply

Thanks a lot

Regards,
Anand