Don't know where to begin
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Don't know where to begin
by mehanathan » Fri Jul 09, 2010 11:35 pm
Hi guys, I'm a noob to verilog HDL. I need to synthesize a radix-2 divider on to an FPGA board. And I do not know where to begin. PLS HELP!!!
- mehanathan
- Posts: 1
- Joined: Wed Jul 07, 2010 3:52 am
- Location: Malaysia
mehanathan
by anand » Fri Jul 23, 2010 12:49 pm
Hi mehanathan 
I suggest you instantiate the divider IP from ISE making use of 'COREGEN'(if you happen to be using Xilinx boards) or an equivalent if you are using Altera boards and Quartus tool.
In 'COREGEN' or it s equivalent in Quartus, you can customize your divider and the tool will generate a HDL instantiation template which you can instantiate in your DSP design.
You can find the method to instantiate in the software manuals of the tool or you can visit the vendors website.
Enjoy your synthesis
I suggest you instantiate the divider IP from ISE making use of 'COREGEN'(if you happen to be using Xilinx boards) or an equivalent if you are using Altera boards and Quartus tool.
In 'COREGEN' or it s equivalent in Quartus, you can customize your divider and the tool will generate a HDL instantiation template which you can instantiate in your DSP design.
You can find the method to instantiate in the software manuals of the tool or you can visit the vendors website.
Enjoy your synthesis
- anand
- Posts: 6
- Joined: Tue May 04, 2010 2:24 pm
- Location: Bangalore
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