fpga4fun.com

Hi all,

How can I convert this piece of verilog description:

Code: Select all

always @(posedge clk) if (&addr) run <= 1'b0; else if (start) run <= 1'b1;


to VHDL:

Code: Select all

process (clk):
begin
  if (rising_edge(clk)) then
    if (????) then
      run <= '0';
    elsif (start = '1') then
      run <= '1';
    end if;
  end if;
end process;


The problem lies in the following expression:
(&addr)

Can someone help me to convert this expression?

Thank you in advance

Thoma

If addr is a bit vector, &addr ANDs all the bits.

I found this site:

http://www.sutherland-hdl.com/online_ve ... f_top.html

If addr is 8 bits, use:

if addr = "11111111" then ...

If not, adjust the number of ones in the constant.

Hi tkbits,

Thanks for your help

So, as addr is a std_logic_vector(5 downto 0), it should be compared to "111111".

Code: Select all

process (clk):
begin
  if (rising_edge(clk)) then
    if (addr = "111111") then
      run <= '0';
    elsif (start = '1') then
      run <= '1';
    end if;
  end if;
end process;

Thoma

how i can write this verilog line in vhdl?

CRC <= CRCinit ? ~0 : ({CRC[30:0],1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7));

Hi fredra,

I would say:

if (CRCinit = 1) then
CRC <= x"FFFFFFFF"
else
CRC <= (CRC(30 downto 0) & '0') xor (CRCinput and x"04C11DB7");
end if;

if it is used in a process.

Thoma

thank you i will try it

i try it and still have problem with

{32{CRCinput}}
because this one is 32 bit
and we have to xor it with 32'h04C11DB7

Fredra,

Could you provide the signal definition for CRCinput?

Thoma

hello Thoma HAUC
i took this from fpga4fun and i'm trying to do it in vhdl

// generate the CRC32
reg [31:0] CRC;
reg CRCflush; always @(posedge clk20) if(CRCflush) CRCflush <= SendingPacket; else if(readram) CRCflush <= (rdaddress==7'h44);
reg CRCinit; always @(posedge clk20) if(readram) CRCinit <= (rdaddress==7);

wire CRCinput = CRCflush ? 0 : (ShiftData[0] ^ CRC[31]);

always @(posedge clk20) if(ShiftCount[0]) CRC <= CRCinit ? ~0 : ({CRC[30:0],1'b0} ^ ({32{CRCinput}} & 32'h04C11DB7));

Fredra,

You can try this.

if (CRCinit = 1) then
CRC <= x"FFFFFFFF"
else
CRC <= (CRC(30 downto 0) & '0') xor ((x"0000000" & "000" & CRCinput) and x"04C11DB7");
end if;

Thoma

hello Thoma HAUC
if you don't mind i'm trying to convert this one to vhdl :

parameter IPsource_1 = 192;
parameter IPsource_2 = 168;
parameter IPsource_3 = 0;
parameter IPsource_4 = 44;

// "IP destination" - put the IP of the PC you want to send to
parameter IPdestination_1 = 192;
parameter IPdestination_2 = 168;
parameter IPdestination_3 = 0;
parameter IPdestination_4 = 2;

// "Physical Address" - put the address of the PC you want to send to
parameter PhysicalAddress_1 = 8'h00;
parameter PhysicalAddress_2 = 8'h07;
parameter PhysicalAddress_3 = 8'h95;
parameter PhysicalAddress_4 = 8'h0B;
parameter PhysicalAddress_5 = 8'hFB;
parameter PhysicalAddress_6 = 8'hAF;

parameter IPchecksum1 = 32'h0000C53F + (IPsource_1<<8)+IPsource_2+(IPsource_3<<8)+IPsource_4+
(IPdestination_1<<8)+IPdestination_2+(IPdestination_3<<8)+(IPdestination_4);
parameter IPchecksum2 = ((IPchecksum1&32'h0000FFFF)+(IPchecksum1>>16));
parameter IPchecksum3 = ~((IPchecksum2&32'h0000FFFF)+(IPchecksum2>>16));

thank you for your time

Hi Fredra,

I can take time to check your VHDL but has not enough time to convert all your Verilog.

Thoma