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hello friends,

I'm not too familiar with verilog so pse be kind with a rookie

How can I initialize some counter to predetermined state? In Altera simulator it starts always with 0 and I need to watch some later event which should synchronize, whatever this counter state.

I tried init statement but no results and as I understand, this is not synthesisable, so actually will be omitted in hardware.

Best regards,

I was told initial was not synthesizable as well, but it certainly is. I use this all the time to set startup values in ISE...

Code: Select all

Initial Begin
Count <= 1;
End


Brad