initial state

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initial state

Postby zuzu » Fri Jul 30, 2010 5:09 pm

hello friends,

I'm not too familiar with verilog so pse be kind :) with a rookie

How can I initialize some counter to predetermined state? In Altera simulator it starts always with 0 and I need to watch some later event which should synchronize, whatever this counter state.

I tried init statement but no results and as I understand, this is not synthesisable, so actually will be omitted in hardware.

Best regards,
zuzu
 
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Re: initial state

Postby Oneironaut » Mon Aug 23, 2010 4:07 am

I was told initial was not synthesizable as well, but it certainly is. I use this all the time to set startup values in ISE...

Code: Select all
Initial Begin
Count <= 1;
End


Brad
Oneironaut
 
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Joined: Tue Oct 21, 2008 6:56 pm


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