CRC module in Verilog

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CRC module in Verilog

Postby shahzadhaider » Sat May 14, 2011 10:55 am

Hello everyone,

I am working on a project in which i had to design a CRC module. I need an 8bit CRC module with 32 bits of data line. I tried some code generators and also tried designing code by myself. I am so close to getting it but there is a problem which is quite solid and I even don't have any kind of idea about it. I can't find anybody to help me out, may be fpga4fun forum could help.

I designed the module, the test bench. I get all the readings but as you know in a CRC module it never stops processing.
Question 1: How do I make it to an end.
Question 2: How do I know that a specific place in wave window is the end.(In one of my code I think it ends at 215ns; sometimes it give me correct result but sometimes don't :( )

Please help me and thanks in advance.
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Re: CRC module in Verilog

Postby hamster » Mon May 16, 2011 12:20 am

A CRC is a stream operation... it has a start (when you assign an initial values) but doesn't end. You have to pick the result that includes the last byte of data byte, but no more - unless you add a "Enable" or "DataPresent" input to the module to tell it when to stop. Depending on your design it will be the cycle that the last data byte is received by the component, or the one immediately after it.

The easy way is to add a signal to your test bench that indicates when all data has been processed. One other way is to frame the data you are interested in checking with easily recognisable values either side - I tend to use all zeros or all ones, so once you process you last byte, set the inputs to all ones. You can then look for then "11111111" values in the trace...
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