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assume I have:

module and1(output y, input a, b);
assign y = a & b;
endmodule

module or1(output y, input a, b);
assign y = a | b;
endmodule

Could both be top modules? I know that we can merge like this:

module mytop(output y1, y2, input a1, a2, b1, b2);
and1 a1(.y(y1), .a(a1), .b(b1));
or1 o1(.y(y2), .a(a2), .b(b2));
endmodule

but this method is too mess, I have to create new top module to support it, any way to have real two top module? Xilinx ISE or Quartus will do.

Thanks much