// Usage of asynchronous resets may negatively impact FPGA resources
// and timing. In general faster and smaller FPGA designs will
// result from not using asynchronous resets. Please refer to
// the Synthesis and Simulation Design Guide for more information.
to my knowledge this is exactly the opposite
your mistake in the code is that the clock enable has to be inside the clock "if"
- Code: Select all
always @(posedge CLK)
if (CLK)
if (RST)
myReg <= 0;
else if (EN)
if (LOAD)
myReg <= D;
else if (DIR)
myReg <= myReg + 1;
else
myReg <= myReg - 1;
or with asynchronous reset (which is smaller when i synthesize it)
- Code: Select all
always @(posedge CLK or posedge RST)
if (RST)
myReg <= 0;
else if (CLK)
if (EN)
if (LOAD)
myReg <= D;
else if (DIR)
myReg <= myReg + 1;
else
myReg <= myReg - 1;