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Hi,
I want to implement fifo on fpga, where the register size is 8 and every register can store 256 words, each word having 32 bits, is there any IP core or i have to do it via verilog???

help is required plez..
thanx

hi misstriker...ryt nw am also working on the same topic "design and implementation of asynchronous FIFO using VHDL" .....i just have learnt VHDL and finding it difficult to implement the logic.can you plz send me the code wid a little bit of explenation...replt plz.

actually, you can find code directly on internet, the code for fifo implementation, but i want to start from the scratch. understand it step by step. i want a boost start.

here is the code i found on internet.

//-----------------------------------------------------
2 // Design Name : syn_fifo
3 // File Name : syn_fifo.v
4 // Function : Synchronous (single clock) FIFO
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module syn_fifo (
8 clk , // Clock input
9 rst , // Active high reset
10 wr_cs , // Write chip select
11 rd_cs , // Read chipe select
12 data_in , // Data input
13 rd_en , // Read enable
14 wr_en , // Write Enable
15 data_out , // Data Output
16 empty , // FIFO empty
17 full // FIFO full
18 );
19
20 // FIFO constants
21 parameter DATA_WIDTH = 8;
22 parameter ADDR_WIDTH = 8;
23 parameter RAM_DEPTH = (1 << ADDR_WIDTH);
24 // Port Declarations
25 input clk ;
26 input rst ;
27 input wr_cs ;
28 input rd_cs ;
29 input rd_en ;
30 input wr_en ;
31 input [DATA_WIDTH-1:0] data_in ;
32 output full ;
33 output empty ;
34 output [DATA_WIDTH-1:0] data_out ;
35
36 //-----------Internal variables-------------------
37 reg [ADDR_WIDTH-1:0] wr_pointer;
38 reg [ADDR_WIDTH-1:0] rd_pointer;
39 reg [ADDR_WIDTH :0] status_cnt;
40 reg [DATA_WIDTH-1:0] data_out ;
41 wire [DATA_WIDTH-1:0] data_ram ;
42
43 //-----------Variable assignments---------------
44 assign full = (status_cnt == (RAM_DEPTH-1));
45 assign empty = (status_cnt == 0);
46
47 //-----------Code Start---------------------------
48 always @ (posedge clk or posedge rst)
49 begin : WRITE_POINTER
50 if (rst) begin
51 wr_pointer <= 0;
52 end else if (wr_cs && wr_en ) begin
53 wr_pointer <= wr_pointer + 1;
54 end
55 end
56
57 always @ (posedge clk or posedge rst)
58 begin : READ_POINTER
59 if (rst) begin
60 rd_pointer <= 0;
61 end else if (rd_cs && rd_en ) begin
62 rd_pointer <= rd_pointer + 1;
63 end
64 end
65
66 always @ (posedge clk or posedge rst)
67 begin : READ_DATA
68 if (rst) begin
69 data_out <= 0;
70 end else if (rd_cs && rd_en ) begin
71 data_out <= data_ram;
72 end
73 end
74
75 always @ (posedge clk or posedge rst)
76 begin : STATUS_COUNTER
77 if (rst) begin
78 status_cnt <= 0;
79 // Read but no write.
80 end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en)
81 && (status_cnt ! = 0)) begin
82 status_cnt <= status_cnt - 1;
83 // Write but no read.
84 end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en)
85 && (status_cnt ! = RAM_DEPTH)) begin
86 status_cnt <= status_cnt + 1;
87 end
88 end
89
90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
91 .address_0 (wr_pointer) , // address_0 input
92 .data_0 (data_in) , // data_0 bi-directional
93 .cs_0 (wr_cs) , // chip select
94 .we_0 (wr_en) , // write enable
95 .oe_0 (1'b0) , // output enable
96 .address_1 (rd_pointer) , // address_q input
97 .data_1 (data_ram) , // data_1 bi-directional
98 .cs_1 (rd_cs) , // chip select
99 .we_1 (1'b0) , // Read enable
100 .oe_1 (rd_en) // output enable
101 );
102
103 endmodule

1. How can i change this code to to make a FIFO of 8*256 , that is the registers are 8 and each register has a depth of 256. total locations= 8*256. and each location can store a 32 bit word. "double converted to binary".

2. I want to implement it on a trigger type of Non-Zero sample and not trigger type of rising edge or falling edge.

Kindly help me out.
thanx

in the above code what is the function of the code
from 9o to 101

???

90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
91 .address_0 (wr_pointer) , // address_0 input
92 .data_0 (data_in) , // data_0 bi-directional
93 .cs_0 (wr_cs) , // chip select
94 .we_0 (wr_en) , // write enable
95 .oe_0 (1'b0) , // output enable
96 .address_1 (rd_pointer) , // address_q input
97 .data_1 (data_ram) , // data_1 bi-directional
98 .cs_1 (rd_cs) , // chip select
99 .we_1 (1'b0) , // Read enable
100 .oe_1 (rd_en) // output enable
101 );

waiting anxiously for reply
thanx

Thnx misstriker...thnx a lot.although its for synchronous FIFO,still the initial build up concept would work.i need a bit of time to analyze this code.i'll inform you later.if you need any additional theoretical info regarding this tell me den.bye.

Lines 90 to 101 instantiate what appears to be a dual port RAM module called ram_dp_ar_aw, and names the instantiation DP_RAM. You set the values of the two parameters DATA_WIDTH and ADDR_WIDTH to set the dual port RAM's width and depth respectively.

r.b.

smgpta!! u r welcom,

thanx reberk, but i have a little of confusion


well if i instantiate this it means i have to define the RAM as well as a seperate module and then instantiate it.

like given below




1 //-----------------------------------------------------
2 // Design Name : syn_fifo
3 // File Name : syn_fifo.v
4 // Function : Synchronous (single clock) FIFO
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module syn_fifo (
8 clk , // Clock input
9 rst , // Active high reset
10 wr_cs , // Write chip select
11 rd_cs , // Read chipe select
12 data_in , // Data input
13 rd_en , // Read enable
14 wr_en , // Write Enable
15 data_out , // Data Output
16 empty , // FIFO empty
17 full // FIFO full
18 );
19
20 // FIFO constants
21 parameter DATA_WIDTH = 8;
22 parameter ADDR_WIDTH = 8;
23 parameter RAM_DEPTH = (1 << ADDR_WIDTH);
24 // Port Declarations
25 input clk ;
26 input rst ;
27 input wr_cs ;
28 input rd_cs ;
29 input rd_en ;
30 input wr_en ;
31 input [DATA_WIDTH-1:0] data_in ;
32 output full ;
33 output empty ;
34 output [DATA_WIDTH-1:0] data_out ;
35
36 //-----------Internal variables-------------------
37 reg [ADDR_WIDTH-1:0] wr_pointer;
38 reg [ADDR_WIDTH-1:0] rd_pointer;
39 reg [ADDR_WIDTH :0] status_cnt;
40 reg [DATA_WIDTH-1:0] data_out ;
41 wire [DATA_WIDTH-1:0] data_ram ;
42
43 //-----------Variable assignments---------------
44 assign full = (status_cnt == (RAM_DEPTH-1));
45 assign empty = (status_cnt == 0);
46
47 //-----------Code Start---------------------------
48 always @ (posedge clk or posedge rst)
49 begin : WRITE_POINTER
50 if (rst) begin
51 wr_pointer <= 0;
52 end else if (wr_cs && wr_en ) begin
53 wr_pointer <= wr_pointer + 1;
54 end
55 end
56
57 always @ (posedge clk or posedge rst)
58 begin : READ_POINTER
59 if (rst) begin
60 rd_pointer <= 0;
61 end else if (rd_cs && rd_en ) begin
62 rd_pointer <= rd_pointer + 1;
63 end
64 end
65
66 always @ (posedge clk or posedge rst)
67 begin : READ_DATA
68 if (rst) begin
69 data_out <= 0;
70 end else if (rd_cs && rd_en ) begin
71 data_out <= data_ram;
72 end
73 end
74
75 always @ (posedge clk or posedge rst)
76 begin : STATUS_COUNTER
77 if (rst) begin
78 status_cnt <= 0;
79 // Read but no write.
80 end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en)
81 && (status_cnt ! = 0)) begin
82 status_cnt <= status_cnt - 1;
83 // Write but no read.
84 end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en)
85 && (status_cnt ! = RAM_DEPTH)) begin
86 status_cnt <= status_cnt + 1;
87 end
88 end
89
90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
91 .address_0 (wr_pointer) , // address_0 input
92 .data_0 (data_in) , // data_0 bi-directional
93 .cs_0 (wr_cs) , // chip select
94 .we_0 (wr_en) , // write enable
95 .oe_0 (1'b0) , // output enable
96 .address_1 (rd_pointer) , // address_q input
97 .data_1 (data_ram) , // data_1 bi-directional
98 .cs_1 (rd_cs) , // chip select
99 .we_1 (1'b0) , // Read enable
100 .oe_1 (rd_en) // output enable
101 );
102
103 endmodule



RAM model is given below


1 //-----------------------------------------------------
2 // Design Name : ram_dp_ar_aw
3 // File Name : ram_dp_ar_aw.v
4 // Function : Asynchronous read write RAM
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module ram_dp_ar_aw (
8 address_0 , // address_0 Input
9 data_0 , // data_0 bi-directional
10 cs_0 , // Chip Select
11 we_0 , // Write Enable/Read Enable
12 oe_0 , // Output Enable
13 address_1 , // address_1 Input
14 data_1 , // data_1 bi-directional
15 cs_1 , // Chip Select
16 we_1 , // Write Enable/Read Enable
17 oe_1 // Output Enable
18 );
19
20 parameter DATA_WIDTH = 8 ;
21 parameter ADDR_WIDTH = 8 ;
22 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
23
24 //--------------Input Ports-----------------------
25 input [ADDR_WIDTH-1:0] address_0 ;
26 input cs_0 ;
27 input we_0 ;
28 input oe_0 ;
29 input [ADDR_WIDTH-1:0] address_1 ;
30 input cs_1 ;
31 input we_1 ;
32 input oe_1 ;
33
34 //--------------Inout Ports-----------------------
35 inout [DATA_WIDTH-1:0] data_0 ;
36 inout [DATA_WIDTH-1:0] data_1 ;
37
38 //--------------Internal variables----------------
39 reg [DATA_WIDTH-1:0] data_0_out ;
40 reg [DATA_WIDTH-1:0] data_1_out ;
41 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
42
43 //--------------Code Starts Here------------------
44 // Memory Write Block
45 // Write Operation : When we_0 = 1, cs_0 = 1
46 always @ (address_0 or cs_0 or we_0 or data_0
47 or address_1 or cs_1 or we_1 or data_1)
48 begin : MEM_WRITE
49 if ( cs_0 && we_0 ) begin
50 mem[address_0] <= data_0;
51 end else if (cs_1 && we_1) begin
52 mem[address_1] <= data_1;
53 end
54 end
55
56 // Tri-State Buffer control
57 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
58 assign data_0 = (cs_0 && oe_0 && ! we_0) ? data_0_out : 8'bz;
59
60 // Memory Read Block
61 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
62 always @ (address_0 or cs_0 or we_1 or oe_0)
63 begin : MEM_READ_0
64 if (cs_0 && ! we_0 && oe_0) begin
65 data_0_out <= mem[address_0];
66 end else begin
67 data_0_out <= 0;
68 end
69 end
70
71 //Second Port of RAM
72 // Tri-State Buffer control
73 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
74 assign data_1 = (cs_1 && oe_1 && ! we_1) ? data_1_out : 8'bz;
75 // Memory Read Block 1
76 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
77 always @ (address_1 or cs_1 or we_1 or oe_1)
78 begin : MEM_READ_1
79 if (cs_1 && ! we_1 && oe_1) begin
80 data_1_out <= mem[address_1];
81 end else begin
82 data_1_out <= 0;
83 end
84 end
85
86 endmodule // End of Module ram_dp_ar_aw


well can i write code without using RAM??

what do you mean by "depth of fifo" and "data width".???

well i have make a fifo which can store a signed fixed point number of 32 and has a binary point of 9. now i want to store 8*256 of such numbers. and each number is of type signed 32 with binary point of 9. what modifications should i make to the code above???


waiting for reply.
thanx

hi misstriker....dude, this one is verilog code basically , i am basically working on VHDL.it wont work for me.i didnt understand the code also

I would not use the code you dredged up on the internet. It has syntax errors when synthesized. It generates latches when you do get it to synthesize, and latches are bad. Finally, the storage element it does instantiate is an asynchronous memory with bidirectional ports. These don't exist on an FPGA as far as I know and I'm not sure what it would synthesize into.

Your best course of action, since it seems you are quite new to this, is to use Coregen in Xilinx or the Megacore generator in Altera to generate a FIFO for you.

If you want to start from scratch, then I would not use this code. I did not, and do not intend to, go over it to see if the logic is correct. So if you do want to use this as a reference, it is at your own risk.

You also need to be clear on your requirements. You say:

I want to implement fifo on fpga, where the register size is 8 and every register can store 256 words, each word having 32 bits, is there any IP core or i have to do it via verilog???

FIFOs have two dimensions not three. They have width and depth. Width is the word length you want to store (i.e. 32 bits in your case) and depth is the number of words you want to store. You say you want to store 256 32-bit words with a register size of 8. That is very unclear. What do you mean by register size? Is this one FIFO of 2K words or 8 FIFOs of 256 words?

And no, a FIFO does not need to be a RAM, but the only other choices are distributed memory or flip flops, and this depends on which vendor you select.

I'd suggest reading application notes from your FPGA vendor, or search on some good papers by Cliff Cummings on FIFO design. They are available on his webpage.

r.b.

r.b
thanks alot for your comments and guidelines. well
as

FIFOs have two dimensions not three. They have width and depth. Width is the word length you want to store (i.e. 32 bits in your case) and depth is the number of words you want to store. You say you want to store 256 32-bit words with a register size of 8. That is very unclear. What do you mean by register size? Is this one FIFO of 2K words or 8 FIFOs of 256 words

well actuallyits a fifo with data width =32,

according to depth , i have to make a FIFO which can store 8*256=2048 words. each word having a width of 32 bits. does it mean i have to use a depth of "2^11" ????


i am using sparten 3E. board.

waiting for reply
thanx

Yes , you will need an 11-bit address bus for your FIFO.

r.b.

FIFO may be used for burst data transfers(burst data transfer in the sense for how many clock cycles the input data is coming)
if B is the burst data written to the FIFO at F1 frequency and
read at F2 frequency and F1>F2 (write freq>read freq)
then, time taken to write to the FIFO = B/F1 ;

data read from the FIFO in this time=(B/F1)* F2;

excess data remained unread in the FIFO = backlog = B- (B/F1)* F2;
(here backlog is the FIFO depth)

again read side may need extra time to read this this excess data which is called MOP UP time and calculated as MOP UP time= backlog / F2
= B(F1-F2)/F1*F2 ;