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hi
I want to have a module with simply this behavioral code:

entity clocking is
Port ( clk1 : in STD_LOGIC;
clk2 : in STD_LOGIC;
result : out STD_LOGIC);
end clocking;

architecture Behavioral of clocking is
begin
process
begin
if( rising_edge(clk1) ) then
result <= '0';
end if;
if( rising_edge(clk2) ) then
result <= '1';
end if;
end process;
end Behavioral;

the pre-synthesis simulation result is fine, but when I try to Synthesis this module an error occur:

"statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition"

which is pointing to the first IF.

I hope the code be clear. I want a module that rising edge of CLK1 results in 0 then rising edge of CLK2 results in 1. this could occur repeatedly.
can some one help me on this problem?

hi ehbas,

a signal that depends on two clocks can be simulated, but not synthesised. The typical solution is to treat one clock as a signal and only use the other clock as clock. Can you tell more about your clocks? frequencies? is there a faster master clock? how timing accurate must result be?

thanks for your reply
well, the clock frequencies are not so important, but they have some delay relative to each other.

The clock frequencies are important to propose you a solution.

Has clk2 always a much higher frequency than clk1?

Can you tell a bit about your project? Where do the clocks come from, where does the result go to?

Two clocks are not appropriate for FPGAs.

Your code is basically describing an S_R latch, only using clocks.

Why not do this?

Code: Select all

process(clk)
begin
  if rising_edge(clk) then
    if R = '1' then
      out <= '0';
    end if;

    if S  = '1' then
      out <= '1';
    end if;
  end if;
end process;


with clock being much faster than S or R?

Case23 wrote:
Has clk2 always a much higher frequency than clk1?

Can you tell a bit about your project? Where do the clocks come from, where does the result go to?

hi, thanks for replies

1. yes, clk2 always has much frequency.

2. as dear tricky mentioned, all I need is a Flip Flop which works with rising_edge of the clocks.

well, about my project:
I have a module which starts its work with rising edge of clk1. there is a 2*1MUX in this design. at the beginning the MUX should select the first input which holds an initiate value for the design process. since the process should repeat(with clk2), the MUX should select the second number for the next times. this process runs for 100 times for instance( clk1_period = 100 * clk2_period ). then the second edge of clk1 arises and initial value changes, and the same story.
so I should control the select pin of the MUX

you should only have 1 clock in your design.
The rest of the design will be logic that is clocked using the source clock. To detect rising edges you compare a registerd version of an input to the input itself and check to see if they are different.

hi,

does the followng code work for you?

Code: Select all

library ieee;
use ieee.std_logic_1164.all;

entity clocking is
   port (
      clk1 : in STD_LOGIC;
      clk2 : in STD_LOGIC;
      result : out STD_LOGIC
   );
end clocking;

architecture Behavioral of clocking is
   signal clk1_delayed : std_logic;
begin

   process(clk2)
   begin
      if clk2'event and clk2 = '1' then
         if (clk1 = '1' and clk1_delayed = '0') then
            result <= '0';
         else
            result <= '1';
         end if;
         clk1_delayed <= clk1;
      end if;
   end process;
end Behavioral;