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i have written code in vhdl for conversion of bit_vector to integer but it gives me result= -2147483648 when simulate in modelsim.when i run it for the first time why???
code for the package is
alupack.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
package aludgn is
function bit_to_int(bits: in bit_vector) return integer;
end package aludgn;

package body aludgn is
function bit_to_int(bits: in bit_vector) return integer is
variable result: integer:=0;
begin
for index in bits'range loop
result := result*2 + bit'pos(bits(index));
end loop;
return result;
end function bit_to_int;
end package body aludgn;
////////////////////////////////////////
alufunc.vhd is
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.aludgn.all;
entity alu is
port(val: in bit_vector;
result: out integer);
end entity alu;
architecture behav of alu is
begin
bv: process is
begin
result<= bit_to_int(val);
wait for 5 ns;
end process bv;
end architecture behav;
//////////////////////////////////////
Test bench for the conversion is alustm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use work.aludgn.all;

entity aludesign is
end entity aludesign;

architecture behav of aludesign is
signal a: bit_vector (3 downto 0);
signal b: integer :=0;
begin
dut: entity work.alu(behav)
port map(a,b);
stim:process is
begin
a<="1010";
wait for 5 ns;
a<="0101";
---wait on a;
end process stim;
end architecture behav;
/////********/////////
code does not give any error while compiling but the problem occurs when i simulate it. it always gives val=0000 and result= -2147483648 on first run why??

B takes the initial value from the component "alu" is driving the value of b, so its initial value of 0 is overriden. The default initial value for everything in VHDL is the leftmost value, in the case of integer is is -2^31 +1

thanks for ur reply please tell me what will be the solution

tricky wrote:B takes the initial value from the component "alu" is driving the value of b, so its initial value of 0 is overriden. The default initial value for everything in VHDL is the leftmost value, in the case of integer is is -2^31 +1

now what should i do for this... i can't get it any more please help