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Hi, anyone got any idea on how am I suppose to edit this coding so that my counter can count up each time by 5 rather than by 1.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity my_counter5 is
port(count: Out std_logic_vector(7 downto 0);
clk: in std_logic;
reset: in std_logic);
end my_counter5;

architecture behav_my_counter5 of my_counter5 is

signal c : std_logic_vector(7 downto 0) := "00000000";

begin

ctr:

process(clk,reset)
variable carry : std_logic_vector(7 downto 0) := "00000000";
begin

if reset'event and(reset = '1') then
c <= (others => '0');

elsif clk'event and (clk = '1') then
--i am adding "00000001" to 'c'.
--this is done using basic logic gates.
-- the equation for full adder is simplified and written below.
--full adder equations are:
-- sum = A xor B xor Carry.
-- carry = (A and B) or (A and carry) or (B and carry).
--subsititue B with "00000001" here and you will get the below equations.
c(0) <= not c(0);
carry(0) := c(0);
c(1)<= c(1) xor carry(0);
carry(1) := c(1) and carry(0);
c(2)<= c(2) xor carry(1);
carry(2) := c(2) and carry(1);
c(3)<= c(3) xor carry(2);
carry(3) := c(3) and carry(2);
c(4)<= c(4) xor carry(3);
carry(4) := c(4) and carry(3);
c(5)<= c(5) xor carry(4);
carry(5) := c(5) and carry(4);
c(6)<= c(6) xor carry(5);
carry(6) := c(6) and carry(5);
c(7)<= c(7) xor carry(6);
carry(7) := c(7) and carry(6);

end if;

end process;

count <= c;

end behav_my_counter5;

try to add "00000101" to c

Try using arithmetic operations rather than building a counter from scratch.

Then you can just use

a <= b + c;

Thanks. May I know how am I suppose to add the 00000101 to c ?

Tricky: I was suppose to edit this coding. So I wonder is there anyway to edit this coding to get the count I want. The +5 I wasn't allow to use.

Or you could count by 1s, and multiply it by 5 with "count <= (counter & "00") +counter;"... just remember that this will generate the first 256 multiples of 5 which is different to mod(n*5, 256) when n > 51.

Hi, I don't really understand what you talking about. Can explain in some other way?

Hi,

If you include the "IEEE.std_logic_unsigned.all" package (as you have) you can use the '+' and '-' much like you would in any other language.

So,

Code: Select all

architecture behav_my_counter5 of my_counter5 is
  signal nextCount : std_logic_vector(7 downto 0);
begin
  -- work out what the next value is to be
  nextCount <= count + 5;

  -- when you see the clock 'tick' update the value.
  process(clk, nextCount)
  begin
     if clk'event and clk ='1' then
        count <= nextCount;
     end if;
  end process;
end behav_my_counter5;


Equally, you can also multiply by five by two leftshifts, and an addition

So,

Code: Select all


architecture behav_my_counter5 of my_counter5 is
  signal count : std_logic_vector(7 downto 0);
  signal nextCount : std_logic_vector(7 downto 0);
begin
  -- work out what the next value is to be
  nextCount <= count + 1;

  -- set the output to being 5 * count (actually implemented as (4*count )+ count)
  output <= (count & "00") + count;

  -- when you see the clock 'tick' update the value.
  process(clk, count)
  begin
     if clk'event and clk ='1' then
        count <= nextCount;
     end if;
  end process;
end behav_my_counter5;


In the later case, output ranges from 0 to 255*5 (= 1275), so output will need to be 11 bits wide. In the earlier example after 255 the output will wrap round to 4 (the remainder of 260 / 5), then go to 9...

hi, Now I understand. But I'm not suppose to use the '+' or '-' in my coding. I only can edit from my older coding.

I think you better re-read the chapter in your text book, or at least maybe http://www.allaboutcircuits.com/vol_4/chpt_2/2.html