Hi, anyone got any idea on how am I suppose to edit this coding so that my counter can count up each time by 5 rather than by 1.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity my_counter5 is

port(count: Out std_logic_vector(7 downto 0);

clk: in std_logic;

reset: in std_logic);

end my_counter5;

architecture behav_my_counter5 of my_counter5 is

signal c : std_logic_vector(7 downto 0) := "00000000";

begin

ctr:

process(clk,reset)

variable carry : std_logic_vector(7 downto 0) := "00000000";

begin

if reset'event and(reset = '1') then

c <= (others => '0');

elsif clk'event and (clk = '1') then

--i am adding "00000001" to 'c'.

--this is done using basic logic gates.

-- the equation for full adder is simplified and written below.

--full adder equations are:

-- sum = A xor B xor Carry.

-- carry = (A and B) or (A and carry) or (B and carry).

--subsititue B with "00000001" here and you will get the below equations.

c(0) <= not c(0);

carry(0) := c(0);

c(1)<= c(1) xor carry(0);

carry(1) := c(1) and carry(0);

c(2)<= c(2) xor carry(1);

carry(2) := c(2) and carry(1);

c(3)<= c(3) xor carry(2);

carry(3) := c(3) and carry(2);

c(4)<= c(4) xor carry(3);

carry(4) := c(4) and carry(3);

c(5)<= c(5) xor carry(4);

carry(5) := c(5) and carry(4);

c(6)<= c(6) xor carry(5);

carry(6) := c(6) and carry(5);

c(7)<= c(7) xor carry(6);

carry(7) := c(7) and carry(6);

end if;

end process;

count <= c;

end behav_my_counter5;