problem: last state not being saved

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problem: last state not being saved

Postby mmina » Mon May 02, 2011 4:01 pm

Hi. I am designing a carry look ahead 8 bit adder. There are 3 roms where the program reads from to obtain the numbers to add
(romA and romB) and another one which contains the type of the equation (A+A, A+B, B-A C - A etc) -> C is the last result . After the result is calculated, it is saved in a register.

Then in the test bench I the address of the numbers (e.g "0000", "0001" -> the numbers are saved in a 16 size array so I selected them by those 4 bits). However, the last result is NOT saved in the register!!! This is code for the register:

Code: Select all
library IEEE;

entity register_c is
    Port ( clk : in std_logic;
           reset : in std_logic;
           write : in std_logic;
            data_in : in std_logic_vector(7 downto 0);
           data_out : out std_logic_vector(7 downto 0));
end register_c;

architecture Behavioral of register_c is

signal temp : std_logic_vector(7 downto 0);

regis : process (clk,write,reset,data_in)

if reset ='0' then
   if (clk'event and clk='1') then
      if write='1' then
         temp <=data_in;
      end if;
   end if;
elsif reset='1' then
    temp <= "00000000";

end if;
end process;

u0: data_out <= temp;
end Behavioral;

Is my way of doing it wrong or is the data of the temp signal lost?
Posts: 1
Joined: Mon May 02, 2011 3:50 pm

Re: problem: last state not being saved

Postby tricky » Wed May 04, 2011 3:54 pm

This is the usual template for a registered process:

Code: Select all
process(clk, reset) --ONLY clock and async reset required here.
  if reset = '1' then
    --do reset
  elsif rising_edge(clk) then
    --do registers
  end if;
end process;

Your code does not follow this template. It probably isnt a problem now, but it may be when things get more complicated.

Other than that, the code you posted doesnt really do a lot. Just registers the input.
Posts: 56
Joined: Wed Dec 09, 2009 11:50 am

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