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Is shown diagram a "good" design result?
Because I see something strange.
In the task I see:
"totatl number of cars is the SUM of previous number and current number."

So it must be Qn = Qn-1 + P

In the diagram I see only:

if (load = '0') then
Qn = P
end if

Which is true?

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity traffic_counter is
port (
reset : in std_logic; -- active high
load : in std_logic; -- active low
sensor : in std_logic;-- on rising edge

p : in std_logic_vector (5 downto 0);
q : out std_logic_vector (5 downto 0);
led : out std_logic

);
end traffic_counter;


architecture test of traffic_counter is

signal counter : unsigned ( 5 downto 0 );
signal p_unsigned : unsigned (5 downto 0);

signal first_time : std_logic; -- to prevent led to be on after reset


begin

p_unsigned <= p;

process (reset,load, sensor, p_unsigned, counter)

begin
if (reset = '1' or counter = 32) then
counter<= "000000";
else
if(load ='0') then
counter <= p_unsigned;
else

if (sensor'event and sensor = '1') then
counter <= counter + 1;
end if;
end if;
end if;
end process;

process(reset, counter)
begin
if (reset = '1') then
first_time <= '1';
else
if (counter = 1) then
first_time <= '0';
end if;
end if;
end process;

q <= counter;

led <= '1' when ( (counter = 0) and (first_time = '0')) else '0';



end test;