What is the meaning of "." in VHDL

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What is the meaning of "." in VHDL

Postby jasonkee » Mon Dec 20, 2010 7:04 am

hi. I came across the dot "." in a testbench. i have no idea what is the function. Normally we will on only see it in the library declaration. However it is used in the process.

Is there anyone know abt it?

Thanks
jasonkee
 
Posts: 12
Joined: Sat Feb 07, 2009 2:18 am

Postby tricky » Mon Dec 20, 2010 9:24 am

it is used to select an element in a record like this:

Code: Select all
type my_record_t is record
  a : integer;
  b : std_logic;
end record my_record_t;

signal r : my_record_t;


...

r.a <= 10;
r.b <= '1';

input <= r.a;
valid <= r.b;

...etc.


Or to dereference a pointer with the .all field (like the * operator in C/C++)

Code: Select all
type my_record_ptr_t is access my_record_t;

variable ptr : my_record_ptr_t;

....
ptr := new my_record_t;

ptr.all := (10, '0');
--or
ptr.all.a := 10;
ptr.all.b := '0';
tricky
 
Posts: 56
Joined: Wed Dec 09, 2009 11:50 am

Postby jasonkee » Tue Dec 21, 2010 8:50 am

It helps. thanks
jasonkee
 
Posts: 12
Joined: Sat Feb 07, 2009 2:18 am


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