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The std_logic/std_logic_vector only rule is an old one. Years ago, at the beginning of synthesisors that understood VHDL, They would only accept std_logic/std_logic_vectors as ports. Because this used to be a rule, it has stuck around like a bad smell and many people still preach this even though support for signed/unsigned/integer/anything came around a long time ago.

As a general rule, stick with an array type at the top level (or any type where you can actually map the bits to individual pins, even record types as long as the internal types can all map to bits) but underneath that, feel free to go mad and use whatever you want. Std_logic, boolean, integer, signed, ufixed, state_type etc etc. It makes coding much much easier when you dont have to do type conversions in every single file!

As an asside, I hope you're refering to signed/unsigned from numeric_std, not from std_logic_arith. std_logic_arith/signed/unsigned are other parts of VHDL that refuse to die.

Jonas wrote:Thanks for the answer. That's good news

As an asside, I hope you're refering to signed/unsigned from numeric_std, not from std_logic_arith. std_logic_arith/signed/unsigned are other parts of VHDL that refuse to die.

Yes.
I am also using in my project some xilinx components from unisim and I saw that they have the use clause for the std_logic_arith/signed/unsigned libraries and sometimes in combinaison with numeric_std.

Jonas

This can be bad news, but only if you actually use signed/unsigned.
Xilinx tend to do stuff the old fashioned way.

No, shouldnt be a problem.

The problem is that std_logic_arith and numeric_std both declare unsigned and signed types. The default behaviour for VHDL when there is a conflict is to make all conflicting types/functions/procdures invisible unless you explicitly specify which one you want:

signal a : ieee.numeric_std.unsigned;
signal b : ieee.std_logic_arith.unsigned;

This would be fine.

signal a : unsigned;
signal b : unsigned;

would cause an error because it doesnt know which unsigned type you want.

numeric_std has been part of the VHDL standard since VHDL 1993.
Std_logic_arith/signed/unsigned were created by synopsis and adopted by other vendors before this, hence why they became so popular.

VHDL 2008 has rolled std_logic_arith/signed/unsigned into the VHDL 2008 standard with two new packages - numeric_std_signed and numeric_std_unsigned. the old packages exist only as a placeholder for the new packages.

But stick with numeric_std if you can!