Need help, Describing State Machine in VHDL

The favorite HDL language in Europe and in Universities

Postby tricky » Tue Nov 16, 2010 3:19 pm

The default state encoding for state machines with more than 4 states is one hot. For <4 states, it will be a 2 bit count. If you want another state encoding, you can specify it via vendor specific attributes.

But yes, it will still work as a state machine.

One point of note - you do not need all signals in a sensitivity list for a clocked process (if you have written the process correctly). Having extra signals in the list slows simulation down.

And if you can look into it - try a 1 process state machine. its much easier to read and you will never create latches.
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