fpga4fun.com

if you write it structurally, you're telling the synthesisor how to do its job. With the c <= a+b; you're letting the synthesisor do what it thinks it is best.

Usually, nowadays, the c <= a + b; form is better as the synthesisor is cleverer than most humans (as well as being more readable).

If in doubt, have a look. Xilinx and Altera have tools to let you look at different view - RTL view, logic view and FPGA fabric veiwer.