error in the testbench for my simple a full-adder(4bit)

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Postby tricky » Tue Nov 16, 2010 10:04 am

Spot the difference:

entity GenAdder4 is
port( Ain, Bin : in std_logic_vector( 3 downto 0 ); ....

component GenAdder4
port( inA, inB : in std_logic_vector( 3 downto 0 ); ...

In the entity you called it Ain, but on the component you called it inA.

The best way to avoid component/entity mismatch is via direct instantiation. This way, you can delete the component bit and just write:

tb : entity work.GenAdder4 port map(....

This way it checks the entity, not the component.
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