[/b]Hello =]

I have to write a VHDL code for 4-bit-adder using the ieee.numeric_std.all package.

so i kinda wrote the beggining but my problem is that i dont know how to add to std_logic_vector(s) a single bit of std_logic (carry in ):

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity ader is

port ( a,b : in std_logic_vector (3 downto 0) ;

carry_in : in std_logic ;

co : buffer std_logic ;

s : buffer std_logic_vector (3 downto 0) );

end ader;

architecture arc_ader of ader is

begin

process (a,b,carry_in)

begin

s<= std_logic_vector ( unsigned (a) + unsigned(b) );

.

.

.

how can i add the carry in this way?

please help