VHDL modeling question

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VHDL modeling question

Postby baseball_man » Mon Oct 11, 2010 5:06 am

Hey guys. I was asked to model a circuit (CRK_2 is the name of the circuit) in VHDL and construct the entity declarations and architecture declarations. The circuit has the following reduced boolean expression: F(not) = (A * B(not)) + (A(not) * C).
Im new at this and my question is could someone please check my work if its correct? I did the work and everything but theres one thing im not certain about. The thing Im not certain about is the (not F) in the architecture/entity part. is that valid they way I wrote it?

Code: Select all
entity CRK_2 is
port(A,B,C: in std_logic;
      (not F):out std_logic);
end CRK_2;

architecture CRK_A of CRK_2 is
(not F) <= (A AND (not B)) OR
                ((not A) AND C);
end CRK_A;

is this valid for the boolean expression that was given?
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