Design a circuit that has the following function:
The output should be ‘1’ if more than half of the inputs are ‘1’.
Input: A (std_logic_vector(7 downto 0))
Output: Z (std_logic)
Can you give some idea?
Design a circuit with VHDL, help again THX
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Design a circuit with VHDL, help again THX
by usbank » Mon Oct 04, 2010 1:40 am
- usbank
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