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hi.. if there is any generic parameters/values in VHDL or verilog to generate RTL, we give the values at the top module..

i wish to know how to generate RTL cores by giving the generic values from any external scripts or command prompt or from visual C++ windows application..

OR

can any tell me, how to interface C language data to VHDL/verilog code, so that data from the C Code can be passed as generic parameters to HDL code modules.