shared signal design

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shared signal design

Postby sinharo » Mon Aug 09, 2010 5:43 am

Hey Everyone,

I have a design question based on the following scenario:

I have signals that are shared between several entities in the design. So,

Entity foo:
<port declarations>

architecture main of foo:
signal f: std_logic_vector
portmap a : e1(f,...)
portmap b : e2(f,...)
portmap c : e3(f,...)
end main

Entity e1:
<port declaration including f>

architecture main of e1:
some code that does f <= f + 1
end main

e2 and e3 are similar to e1.

The processes inside e1, e2, and e3 are not run in parallel. This is done using some state machine not shown here. So the assignments to f are never happening in more than 1 place. But, vhdl will probably not allow me to do this saying that f is written by multiple writers.

My question is: How do I implement this? How should f be declared since it is input and output to other entities. I know there is a state machine that will prevent multiple concurrent writes, but how can I make VHDL recognize this fact? Any help will greatly appreciated!

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Joined: Sun Aug 08, 2010 4:53 pm

Postby tricky » Mon Aug 09, 2010 7:53 am

a signal is just a wire.

A wire can only be driven from one place, unless it is a tri-state bus. So whilst what you are trying to do will cause te signal to place 'X's on the signal in VHDL simulation (multiple drivers) its actually not realistic hardware either.

The basic answer to your question: You cannot do what you are trying to do. Unless your state machine drives 'Z' on to the signal when it is not driving the signal, you are going about things the wrong way. If you're on an FPGA, driving 'Z' is only valid for output pins, not between entities.

So, what are you actually trying to do? Are you drawing out the circuit diagram before writing a word of VHDL? VHDL is NOT a programming language.
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Joined: Wed Dec 09, 2009 11:50 am

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