fpga4fun.com

Looks very interesting. Thanks for putting that online. I just looked at the CPLD code and it seems pretty straighforward. It seems from your comments that you worked more on the FX2 than the CPLD. Was the CPLD tested in hardware?

I also digged into the FX2 code. I'm trying the code as-is, although I'll have to change the PortC to something else (I'm using the 56 pins version of the chip) and I'll want to simulate an FTDI chip eventually.

Ok, getting very close. I'm trying to see if I can get the USB-Blaster emulation working.

I had a problem that the board would not re-enumerate. I had to add this line to the TD_Init routine.
Rwuen = TRUE;

Now it re-enumerates (most of the time... sometimes it doesn't, will have to work on that later) and asks for a driver. Next was to update the descriptor and EEPROM files... not sure if I got that 100% right but Quartus detects a USB-BLASTER!

Next I updated the PortC to PortD in the code, with the right pins for my board, wasn't too hard. Now I don't see any activity on the JTAG lines... and Quartus says "Can't access JTAG chain". But hopefully I'm close.

This one is much simpler http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

It seems that the WAKEUP pin should be high for the re-numeration to work reliably. I also found why my IOs weren't toggling (I'm using PD8..15 so I had to put FD in 8-bits mode) - now I can see IO activity when Quartus detects the JTAG hardware. But Quartus hangs there. Probably another small mistake somewhere.

Found the mistake - this thing works!

The FX2 is amazing, being able to emulate a USB-Blaster (FTDI + CPLD) with a completely soft solution.

I tried your files on Saxo/Xylo. I used the PortD instead of PortC, the changes are shown below. Feel free to include them into your file distribution.

I found that the EEPROM content is not required (EEPROM.c file) and the content can be replace by all 0's.

In usbjtag.c, put
sbit TDI = 0xB0+4; // high nibble of PortD
sbit TDO = 0xB0+6;
sbit TCK = 0xB0+5;
sbit TMS = 0xB0+7;
#define bmTDIOE bmBIT4
#define bmTDOOE bmBIT6
#define bmTCKOE bmBIT5
#define bmTMSOE bmBIT7
...
IFCONFIG = 3;
EP2FIFOCFG = 0x04;
EP4FIFOCFG = 0x04;
EP6FIFOCFG = 0x04;
EP8FIFOCFG = 0x04;
OED = bmTDIOE | bmTCKOE | bmTMSOE;
// remove any reference to PortE
...
BOOL DR_VendorCmnd(void)
{
if(SETUPDAT[1] == 0x90) // READ EEPROM
{
EP0BUF[0] = 0; // EPROM content is actually not required
EP0BUF[1] = 0;
...

In shift.a51, use
TDI BIT 0B0H+4H
TDO BIT 0B0H+6H
TCK BIT 0B0H+5H
TMS BIT 0B0H+7H

Finally if you want to emulate the USB-Blaster, you can change the dscr.a51
dw 0FB09H ;; Vendor ID 0x09FB
dw 00160H ;; Product ID 0x6001
and update the StringDscr2 to "USB-Blaster" (vendor can be anything)

I'm not sure how good is the FTDI solution with their "Multi-Protocol Synchronous Serial Engine (MPSSE)"
http://www.ftdichip.com/Projects/MPSSE.htm#JTAG

But I like the idea of using an FX2 - it's soft so very easily upgradable.

As for the SOPC JTAG, that's proprietary Altera. Too bad because they have a good JTAG solution compared to Xilinx. SignalTap is superior to Chipscope too in my opinion (better integrated to their software suite).

Would I be correct in saying that the JTAG pins of the FPGA are not connected to the FX2 on the Xylo boad at present?
I recently purchased the Xylo and I wouldn't mind giving this USB-Blaster firmware a shot...

Yes, you have to solder 4 wires from the FX2 chip to the JTAG connector. I used the FX2 pin 56, pin 1, 2 and 3 (PortD) as you can deduct from the code above.

Also make sure WAKEUP is high (there is a resistor strap option on the back of the board).

The new Xylo-EM board (announced today) is pre-wired for this project, no need to solder the 4 wires anymore!

I kept the JTAG connector, for those you still want to use an external JTAG cable (or for those who need to use JTAG & USB-2 at the same time).

Hello,

I am a student working for an university. We want to develop
the same firmware (USB-JTAG connection) for an home-made Altera Cyclone2 board.

We want to replace the Altera USB-Blaster solution by an FX2 directly connected to the JTAG ports of the FPGA.

I just have some questions about your solution FPGA4Fun. Please,
can i contact you or could you give me your whole project?

THANK YOU.

Finally it works , it was just a problem of cable connectic

Will do. I'm quite busy with my new ARM board so I'll do it in a little while.

I see that you are playing with the Xilinx Platform Cable USB now. Too bad this one has a CPLD, but I guess it allows faster JTAG communication.

Is it ok to use SDCC to compile FX2 usb firmware? Or is there some reason to use the evaluation compiler?

I tried on Windows and run a make. Got a "basename: command not found"... I guess I need to install cygwin.

Almost, now I get a "C:\Program: C:\Program: No such file or directory"
It may not like a path with spaces.