fpga4fun.com

I got it to work!
I found that I had to remove the @echo command...

I'm not sure which files I need to modify to try on one of my boards.

hw_basic.c
I probably have to set all the defines to 0
#define HAVE_PS_MODE 0
#define HAVE_AS_MODE 0
#define HAVE_OE_LED 0
and overwrite the sbit definitions, and update the ProgIO_Init(void)

hw_xpcu_i.c
Do I have to also update the defines?
Also have #define HAVE_OE_LED 0 instead of 1

hw_xpcu_x.c
Use #define HAVE_OE_LED 0 ?

usbjtag.c
In void usb_jtag_init(void), I need to change the EPxCFG settings.

I created an hw_saxo_l.c file, commented the first 3 defines, and updated the sbit definitions. I also updated the void ProgIO_Init(void) (I don't use portE for power, and I use portD instead of portC)

In usbjtag.c, I changed all the EPxFIFOCFG to 0x04, so that portD can be used as IO.

I also changed dscr.a51 to simulate a USB-Blaster. Maybe that's where I screwed up, the board beeps three times after re-numeration.

So..what is the actual status of the Cypress FX2 solution now?

Is it really recognized as USB Blaster under Quartus?
And how about firmware loading under Windows?

I have ordered some FX2 samples from Cypress and will make an opensouorce schematic and PCB design so others can benefit as well...


cheers
rick

Sure it works great, you can make the FX2 look like a USB-Blaster.
Firmware loading is done through a Cypress utility that you can download from Cypress website.

Kuul (o;


And you used the TSOP56 package as well I saw...
Have you any difference besides pinout from the original code?


So I guess it's time to do schematic and layout...
good excersize to see if PADS2007 evaluation version is
enough for this...


cheers
rick

I had some code differences but I posted them in this topic. It was due to the different ports I am using.

Just received my ECP2 Mico32 board today from Lattice...

And what they're using for USB programming? The CY7C68013A of course, but with a MachXO in between (o;


Oh...Cypress also deliverd 3 CY7C68013A samples which I ordered 2 nights ago (o;


cheers
rick

Hi!

I'm currently also building this great project, with the FTDI chip and the CPLD. The problem is: Quartus hangs when I plug in the home-brew USB blaster. Can someone tell what what I am doing wrong? I already checked all connections, verified the CPLD (I'm using a 7064AETC-44) My target is a Pluto 3 board.

I hope you can help me.

Danny.

Does this software let you program the xylo fpga over fx2 usb?

Yes, it does, although on Xylo, a modification is required (4 wires to solder).

So I can program and debug if I do this modification, otherwise I can only program? I'll look closely at this code before asking which 4 wires go where.

Yes, it makes the FX2 simulate a USB-blaster, so you can control the FPGA from Quartus.
Quartus has SignalTap, which allows to get a virtual logic analyzer inside the FPGA - very nice!

Hi, I have a new Xylo-L board, and I would like to use the usb_jtag software with it. I have read through this thread and have a few questions.

1) On the Xylo-L board, are the JTAG connections the same as mentioned previously ? i.e.,

port D.4 = TDI
port D.5 = TCK
port D.6 = TDO
port D.7 = TMS

2) If so, shouldn't the ports be enabled, instead of the FIFO in the IFCONFIG register ?

i.e., IFCONFIG = 0

In one post you (fpga4fun) had IFCONFIG=3, which would disable port D.

3) On the Xylo-L board, does this JTAG chain include both the Spartan3 FPGA and the LPC2132 ARM CPU ? Which one comes first ?

Actually there are two JTAG chains on Xylo-L, one of the FPGA and one for the LPC.

The port D and the FIFO can be enabled together, because Xylo-L uses the FIFO in 8-bits mode, so port D is free.

Do you want to use usb-JTAG with the FPGA or with the LPC?

fpga4fun wrote:The port D and the FIFO can be enabled together, because Xylo-L uses the FIFO in 8-bits mode, so port D is free.

Okay, I get it. That's a nice advantage to an 8-bit wide FIFO.

fpga4fun wrote:Actually there are two JTAG chains on Xylo-L, one of the FPGA and one for the LPC.

Do you want to use usb-JTAG with the FPGA or with the LPC?

Actually, I think I answered my own question using a multimeter ;-} I got the following :

D.0 FPGA TCK
D.1 FPGA TDO
D.2 FPGA TDI
D.4 FPGA TMS

D.3 LPC TMS
D.5 LPC TCK
D.6 LPC TDI
D.7 LPC TDO

Is this right ?

Looks good.

Hello guys.

Im trying to make a custom USB-JTAG Board using the FX2, and i have some problems with it.

My pc views perfectly the FX2 as an ALTERA-BLASTER, after i uploaded the firmware etc.

When i run Quartus, and i start to detect (into the Hardware Setup into the Programmer Window), Quartus does not respond, it becames "time out", and i have to finish the program with the task manager.

But if i try with the evaluation board (SAXO-L rev.A), Quartus works perfectly.

Well, i don't know what i am doing wrong with the FX2.

I tried with and without EPROM (the pull-up resitors are always on at the I2C pins).

All the GNDs and VCCs are connected, the USB wires are ok, and i am using the PD0...PD3 like the original board.

There aren't shortmakes, my board is not damage... just i checked all the electrical parts, and everything is ok.

Well hehe, i am open for everything.... thx guys for your answers

Make sure the FX2 pin WAKEUP is high. It's probable not the reason, but it is high on Saxo-L.

Yes, thx for your quick answer.

WAKEUP is HIGH and RESERVED is GROUND.

Any special config for talk over the PD0...PD3 ?

Im using an external 24MHz clock too (I use only the clk IN). The Saxo is using a resonator one using boths.

Kawk, Thanks for your great work!!

Now, I changed source code as fpga4fun did and work well. I changed VID,PID (09FB, 6001), so it can be renumerated as usb-blaster. I saw you said that it can be usb-jtag-if have its own VID PID, but i can't find any driver for windows. so if i use your VID,PID, how can setup device?


Thanks!

I know this is probably a 'no' but is it technically possibly to port this to a usb 1.1 chip?

I want to know about the bit download speed using FX2 usb-jtag (Compared to using FTDI chips).
Thanks!