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hi friends.
ı have this term VHDL lesson in my uni and ı got a project about frequency counter...
ı will use spartan3 board to show it worked...when ı put the oscilator the necessary input, LCD display will show it's frequency...
and ı will use spartan3 board's 50Mhz oscilator to synchronize the oscilator's frequency which ı wanna learn...ı have to use counters (metastability circuit,edge dedector etc.. for these)..ı am trying on it but ı can do nothing..
if u have source code for this project can u send me or can u tell me how can ı do this?????this is my last lesson to graduate and it depends to this project..
thanks....

The whole point is that if there is something wrong with you or your university you should fail. That way we don't get people designing aeroplanes that fall out of the sky for no reason.

You have given us nothing and ask for a complete project. That is not polite. If you don't know what you are doing then learn and ask specific questions.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity freqmeter is
Port ( FTEST : in STD_LOGIC;
FANA : in STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
NOKTA : out STD_LOGIC;
FREKANS : out STD_LOGIC_VECTOR (6 downto 0));
end freqmeter;

architecture Behavioral of freqmeter is

signal DONGU : integer range 0 to 49999999 ;
signal I : integer range 0 to 49999999 ;
signal counter: integer range 0 to 49999999 ;
signal saniye : STD_LOGIC ;
signal Q : STD_LOGIC ;

begin

process(FANA)
begin
if (rising_edge(FANA)) then
for I in 0 to 49999999 loop
DONGU <= DONGU+1;
end loop;
saniye <= '1' ;
end if;
end process;

process(FTEST)
begin
if (rising_edge(FTEST)) then
Q <= saniye ;
end if;
if(Q = '1') then
counter <= counter+1 ;
else
counter <= 0 ;
end if;

end process;
end Behavioral;



ı have written..according to way of thinking me ; when ı send the last value of counter to a register then, ı will be found the unknown frequency...but ı gave this error report while ı want to see view synthesis report : FATAL_ERROR:HDLSynthesis:Portability/export/Port_Main.h:127:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at http://www.xilinx.com/support.

ı have looked at he http://www.xilinx.com/support. but ı could not find anything..
what does this mean can u help me..

friends ı have solved the problem...
for I in 0 to 49999999 loop
DONGU <= DONGU+1;
end loop;

this part of the code was making the system asynchronous ...
ı am very wonderful, are not I?

anyway, ı think ı will need your helps again to send the data spartan3e board and ı will ask about it to u ...
thanks...follow this topic please