Hi,
I am a user of Xilinx Spartan-3, I am confused about "primitive" and "macro".
For example in the schematic library, DCM (Digital Clock Manager) is considered as "Primitive", while M2_1 (2-to-1 Multiplexer) is a "Macro". Can anyone explain?
Or does my question make sense at all?
Primitive v.s. Macro
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Primitive v.s. Macro
by eleleesp » Sat Aug 12, 2006 10:37 am
- eleleesp
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by tkbits » Wed Aug 16, 2006 11:27 pm
I have not found a way to use the macros in VHDL or Verilog code.
If I use schematic entry, each schematic file is translated into VHDL or Verilog code, determined by "design flow". For every schematic that uses a macro, that macro will produce definition code for a VHDL entity or a Verilog module.
If I use schematic entry, each schematic file is translated into VHDL or Verilog code, determined by "design flow". For every schematic that uses a macro, that macro will produce definition code for a VHDL entity or a Verilog module.
- tkbits
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- Joined: Mon Aug 02, 2004 10:36 pm
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